diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c
index 3e3d2520e2..7bdf71d9cf 100644
--- a/src/mainboard/amd/torpedo/BiosCallOuts.c
+++ b/src/mainboard/amd/torpedo/BiosCallOuts.c
@@ -18,7 +18,7 @@
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include "Hudson-2.h"
 #include <stdlib.h>
-#include <southbridge/amd/cimx/sb700/gpio_oem.h>
+#include <southbridge/amd/cimx/sb900/gpio_oem.h>
 
 static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
 static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr);
diff --git a/src/southbridge/amd/cimx/sb900/gpio_oem.h b/src/southbridge/amd/cimx/sb900/gpio_oem.h
index b6bde9fdd5..f3ab5586a7 100644
--- a/src/southbridge/amd/cimx/sb900/gpio_oem.h
+++ b/src/southbridge/amd/cimx/sb900/gpio_oem.h
@@ -3,7 +3,7 @@
 
 /* Hudson-2 ACPI PmIO Space Define */
 #define SB_ACPI_BASE_ADDRESS              0x0400
-#define ACPI_MMIO_BASE  ((u8 *)0xFED80000)
+#define VACPI_MMIO_BASE  ((u8 *)0xFED80000)
 #define SB_CFG_BASE     0x000   // DWORD
 #define GPIO_BASE       0x100   // BYTE
 #define SMI_BASE        0x200   // DWORD
@@ -43,4 +43,11 @@
 #define Mmio32( BaseAddr, Register ) \
   *Mmio32Ptr( BaseAddr, Register )
 
+#define SB_GPIO_REG01   1
+#define SB_GPIO_REG02   2
+#define SB_GPIO_REG15   15
+#define SB_GPIO_REG24   24
+#define SB_GPIO_REG25   25
+#define SB_GPIO_REG27   27
+
 #endif