src: Add missing 'void' in function definition

Change-Id: I7fa1f9402b177a036f08bf99c98a6191c35fa0b5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/cpu/x86/smm/smm_module_handler.c

@@ -193,8 +193,8 @@ RMODULE_ENTRY(smm_handler_start);
  * are linked at. */
 int __weak mainboard_io_trap_handler(int smif) { return 0; }
 void __weak cpu_smi_handler(void) {}
-void __weak northbridge_smi_handler() {}
+void __weak northbridge_smi_handler(void) {}
-void __weak southbridge_smi_handler() {}
+void __weak southbridge_smi_handler(void) {}
 void __weak mainboard_smi_gpi(u32 gpi_sts) {}
 int __weak mainboard_smi_apmc(u8 data) { return 0; }
 void __weak mainboard_smi_sleep(u8 slp_typ) {}

src/device/oprom/yabel/pmm.c

@@ -104,7 +104,7 @@ u8 pmm_setup(u16 segment, u16 offset)
 /* handle the selfdefined interrupt, this is executed, when the PMM Entry Point
  * is executed, it must handle all PMM requests
  */
-void pmm_handleInt()
+void pmm_handleInt(void)
 {
 	u32 rval = 0;
 	u16 function, flags;

src/northbridge/intel/gm45/iommu.c

@@ -8,7 +8,7 @@
 
 #include "gm45.h"
 
-void init_iommu()
+void init_iommu(void)
 {
 	/* FIXME: proper test? */
 	int me_active = pci_read_config8(PCI_DEV(0, 3, 0), PCI_CLASS_REVISION) != 0xff;

src/soc/amd/cezanne/config.c

@@ -4,7 +4,7 @@
 #include <device/device.h>
 #include "chip.h"
 
-const struct soc_amd_common_config *soc_get_common_config()
+const struct soc_amd_common_config *soc_get_common_config(void)
 {
 	/* config_of_soc calls die() internally if cfg was NULL, so no need to re-check */
 	const struct soc_amd_cezanne_config *cfg = config_of_soc();

src/soc/amd/picasso/config.c

@@ -4,7 +4,7 @@
 #include <device/device.h>
 #include "chip.h"
 
-const struct soc_amd_common_config *soc_get_common_config()
+const struct soc_amd_common_config *soc_get_common_config(void)
 {
 	/* config_of_soc calls die() internally if cfg was NULL, so no need to re-check */
 	const struct soc_amd_picasso_config *cfg = config_of_soc();

src/soc/amd/sabrina/config.c

@@ -6,7 +6,7 @@
 #include <device/device.h>
 #include "chip.h"
 
-const struct soc_amd_common_config *soc_get_common_config()
+const struct soc_amd_common_config *soc_get_common_config(void)
 {
 	/* config_of_soc calls die() internally if cfg was NULL, so no need to re-check */
 	const struct soc_amd_sabrina_config *cfg = config_of_soc();

src/soc/samsung/exynos5420/usb.c

@@ -16,13 +16,13 @@ static void reset_dwc3(struct exynos5_usb_drd_dwc3 *dwc3)
 	setbits32(&dwc3->usb2phycfg, 0x1 << 31);	/* PHY soft reset */
 }
 
-void reset_usb_drd0_dwc3()
+void reset_usb_drd0_dwc3(void)
 {
 	printk(BIOS_DEBUG, "Starting DWC3 reset for USB DRD0\n");
 	reset_dwc3(exynos_usb_drd0_dwc3);
 }
 
-void reset_usb_drd1_dwc3()
+void reset_usb_drd1_dwc3(void)
 {
 	printk(BIOS_DEBUG, "Starting DWC3 reset for USB DRD1\n");
 	reset_dwc3(exynos_usb_drd1_dwc3);
@@ -58,13 +58,13 @@ static void setup_dwc3(struct exynos5_usb_drd_dwc3 *dwc3)
 		0x1 << 12);	/* port capability HOST */
 }
 
-void setup_usb_drd0_dwc3()
+void setup_usb_drd0_dwc3(void)
 {
 	setup_dwc3(exynos_usb_drd0_dwc3);
 	printk(BIOS_DEBUG, "DWC3 setup for USB DRD0 finished\n");
 }
 
-void setup_usb_drd1_dwc3()
+void setup_usb_drd1_dwc3(void)
 {
 	setup_dwc3(exynos_usb_drd1_dwc3);
 	printk(BIOS_DEBUG, "DWC3 setup for USB DRD1 finished\n");
@@ -121,14 +121,14 @@ static void setup_drd_phy(struct exynos5_usb_drd_phy *phy)
 	clrbits32(&phy->clkrst, 0x1 << 1);  /* deassert port reset */
 }
 
-void setup_usb_drd0_phy()
+void setup_usb_drd0_phy(void)
 {
 	printk(BIOS_DEBUG, "Powering up USB DRD0 PHY\n");
 	setbits32(&exynos_power->usb_drd0_phy_ctrl, POWER_USB_PHY_CTRL_EN);
 	setup_drd_phy(exynos_usb_drd0_phy);
 }
 
-void setup_usb_drd1_phy()
+void setup_usb_drd1_phy(void)
 {
 	printk(BIOS_DEBUG, "Powering up USB DRD1 PHY\n");
 	setbits32(&exynos_power->usb_drd1_phy_ctrl, POWER_USB_PHY_CTRL_EN);

src/southbridge/amd/cimx/sb800/spi.c

@@ -32,7 +32,7 @@ static void execute_command(void)
 	       (read8((void *)(spibar+3)) & 0x80));
 }
 
-void spi_init()
+void spi_init(void)
 {
 	struct device *dev;