Documentation/soc/intel/fsp/ppi: Document new feature to dispatch external PPI

Some new feature added into FSP specification to perform dispatching
of external PPI service from boot firmware (coreboot) to FSP.

Change-Id: Iaf6b54ccd27e21860539bb2a9966054fdb027108
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31839
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2019-03-11 16:01:20 +05:30
parent 52331ba4f7
commit ebac8c772f
2 changed files with 13 additions and 0 deletions

View File

@ -11,3 +11,7 @@ This section contains documentation about Intel-FSP in public domain.
* [FSP Specification 1.1](https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf) * [FSP Specification 1.1](https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf)
* [FSP Specification 2.0](https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v2.pdf) * [FSP Specification 2.0](https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v2.pdf)
## Additional Features in FSP 2.1 specification
- [PPI](ppi/ppi.md)

View File

@ -0,0 +1,9 @@
# PEIM to PEIM Interface (PPI)
This section is intended to document the purpose of creating PPI service
inside coreboot space to perform some specific operation related to CPU,
chipset using Intel FSP. This feature is added into FSP specification 2.1
where FSP should be able to locate PPI, published by boot firmware and
able to execute the same in FSP's context.
* [What is PPI](https://www.intel.com/content/dam/www/public/us/en/documents/reference-guides/efi-pei-cis-v09.pdf)