From ebb645a9fb5d81a8ea701fd53a2bf63bb899d51c Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Fri, 25 Jul 2003 03:05:54 +0000 Subject: [PATCH] YhLu's changes to resolve several memory and other problems. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1036 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/include/device/pci_ids.h | 4 + src/mainboard/tyan/s2880/auto.c | 560 ++++++------------- src/mainboard/tyan/s2880/failover.c | 32 +- src/northbridge/amd/amdk8/coherent_ht.c | 122 +++- src/northbridge/amd/amdk8/raminit.c | 23 +- src/southbridge/amd/amd8111/Config.lb | 1 + src/southbridge/amd/amd8131/amd8131_bridge.c | 13 +- 7 files changed, 334 insertions(+), 421 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 6b638fef18..947bc6f6e4 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -411,6 +411,10 @@ #define PCI_DEVICE_ID_AMD_8111_SMB 0x746a #define PCI_DEVICE_ID_AMD_8111_ACPI 0x746b +#define PCI_DEVICE_ID_AMD_8111_USB2 0x7463 +#define PCI_DEVICE_ID_AMD_8131_PCIX 0x7450 +#define PCI_DEVICE_ID_AMD_8131_IOAPIC 0x7451 + #define PCI_VENDOR_ID_TRIDENT 0x1023 #define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000 #define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX 0x2001 diff --git a/src/mainboard/tyan/s2880/auto.c b/src/mainboard/tyan/s2880/auto.c index 0612989337..e09662223c 100644 --- a/src/mainboard/tyan/s2880/auto.c +++ b/src/mainboard/tyan/s2880/auto.c @@ -1,437 +1,211 @@ #define ASSEMBLY 1 #include #include -#include "arch/romcc_io.h" +#include +#include +#include #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" #include "northbridge/amd/amdk8/early_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -/* -#warning "FIXME move these delay functions somewhere more appropriate" -#warning "FIXME use the apic timer instead it needs no calibration on an Opteron it runs at 200Mhz" -static void print_clock_multiplier(void) +#include "cpu/k8/apic_timer.c" +#include "lib/delay.c" +#include "cpu/p6/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "debug.c" + +static void memreset_setup(void) { - msr_t msr; - print_debug("clock multipler: 0x"); - msr = rdmsr(0xc0010042); - print_debug_hex32(msr.lo & 0x3f); - print_debug(" = 0x"); - print_debug_hex32(((msr.lo & 0x3f) + 8) * 100); - print_debug("Mhz\r\n"); + /* Set the memreset low */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); + /* Ensure the BIOS has control of the memory lines */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); } -static unsigned usecs_to_ticks(unsigned usecs) +static void memreset(int controllers, const struct mem_controller *ctrl) { -#warning "FIXME make usecs_to_ticks work properly" -#if 1 - return usecs *2000; -#else - // This can only be done if cpuid says fid changing is supported - // I need to look up the base frequency another way for other - // cpus. Is it worth dedicating a global register to this? - // Are the PET timers useable for this purpose? - - msr_t msr; - msr = rdmsr(0xc0010042); - return ((msr.lo & 0x3f) + 8) * 100 *usecs; -#endif + udelay(800); + /* Set memreset_high */ + outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); + udelay(90); } -static void init_apic_timer(void) +static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) { - volatile uint32_t *apic_reg = (volatile uint32_t *)0xfee00000; - uint32_t start, end; - // Set the apic timer to no interrupts and periodic mode - apic_reg[0x320 >> 2] = (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0); - // Set the divider to 1, no divider - apic_reg[0x3e0 >> 2] = (1 << 3) | 3; - // Set the initial counter to 0xffffffff - apic_reg[0x380 >> 2] = 0xffffffff; + /* Routing Table Node i + * + * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c + * i: 0, 1, 2, 3, 4, 5, 6, 7 + * + * [ 0: 3] Request Route + * [0] Route to this node + * [1] Route to Link 0 + * [2] Route to Link 1 + * [3] Route to Link 2 + * [11: 8] Response Route + * [0] Route to this node + * [1] Route to Link 0 + * [2] Route to Link 1 + * [3] Route to Link 2 + * [19:16] Broadcast route + * [0] Route to this node + * [1] Route to Link 0 + * [2] Route to Link 1 + * [3] Route to Link 2 + */ + + uint32_t ret=0x00010101; /* default row entry */ + + static const unsigned int rows_2p[2][2] = { + { 0x00050101, 0x00010404 }, + { 0x00010404, 0x00050101 } + }; + + if(maxnodes>2) { + print_debug("this mainboard is only designed for 2 cpus\r\n"); + maxnodes=2; + } + + + if (!(node>=maxnodes || row>=maxnodes)) { + ret=rows_2p[node][row]; + } + + return ret; } -static void udelay(unsigned usecs) +static inline int spd_read_byte(unsigned device, unsigned address) { -#if 1 - uint32_t start, ticks; - tsc_t tsc; - // Calculate the number of ticks to run for - ticks = usecs_to_ticks(usecs); - // Find the current time - tsc = rdtsc(); - start = tsc.lo; - do { - tsc = rdtsc(); - } while((tsc.lo - start) < ticks); -#else - volatile uint32_t *apic_reg = (volatile uint32_t *)0xfee00000; - uint32_t start, value, ticks; - // Calculate the number of ticks to run for - ticks = usecs * 200; - start = apic_reg[0x390 >> 2]; - do { - value = apic_reg[0x390 >> 2]; - } while((start - value) < ticks); -#endif + return smbus_read_byte(device, address); } -static void mdelay(unsigned msecs) -{ - int i; - for(i = 0; i < msecs; i++) { - udelay(1000); - } -} - -static void delay(unsigned secs) -{ - int i; - for(i = 0; i < secs; i++) { - mdelay(1000); - } -} - -static void memreset_setup(const struct mem_controller *ctrl) -{ - // Set the memreset low - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); - // Ensure the BIOS has control of the memory lines - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); - print_debug("memreset lo\r\n"); -} - -static void memreset(const struct mem_controller *ctrl) -{ - udelay(800); - // Set memreset_high - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); - print_debug("memreset hi\r\n"); - udelay(50); -} -*/ +#include "northbridge/amd/amdk8/cpu_ldtstop.c" +#include "southbridge/amd/amd8111/amd8111_ldtstop.c" #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "sdram/generic_sdram.c" -#define NODE_ID 0x60 -#define HT_INIT_CONTROL 0x6c - -#define HTIC_ColdR_Detect (1<<4) -#define HTIC_BIOSR_Detect (1<<5) -#define HTIC_INIT_Detect (1<<6) - -#define APIC_DEFAULT_BASE 0xfee00000 - -#define APIC_ID 0x020 - -static int boot_cpu(void) +static void enable_lapic(void) { - volatile unsigned long *local_apic; - unsigned long apic_id; - int bsp; - int apicEn; msr_t msr; msr = rdmsr(0x1b); - bsp = !!(msr.lo & (1 << 8)); - apicEn = !!(msr.lo & (1<<11)); - if(apicEn) { - print_debug("apic enabled\r\n"); - } else { - msr.lo |= (1<<11); - wrmsr(0x1b,msr); - } - apic_id = *((volatile unsigned long *)(APIC_DEFAULT_BASE+APIC_ID)); - print_debug("apic_id: "); - print_debug_hex32(apic_id>>24); - print_debug("\r\n"); - - if (bsp) { - print_debug("Bootstrap cpu\r\n"); - } else { - print_debug("Application processor\r\n"); - // asm("hlt"); // move to end before halt should notify BSP - // if you start AP in coherent.c you can just stop it here - } - - return bsp; + msr.hi &= 0xffffff00; + msr.lo &= 0x000007ff; + msr.lo |= APIC_DEFAULT_BASE | (1 << 11); + wrmsr(0x1b, msr); } -static int cpu_init_detected(void) +static void stop_this_cpu(void) { - unsigned long dcl; - int cpu_init; + unsigned apicid; + apicid = apic_read(APIC_ID) >> 24; - unsigned long htic; + /* Send an APIC INIT to myself */ + apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); + apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT); + /* Wait for the ipi send to finish */ + apic_wait_icr_idle(); - htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); -#if 0 - print_debug("htic: "); - print_debug_hex32(htic); - print_debug("\r\n"); + /* Deassert the APIC INIT */ + apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); + apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); + /* Wait for the ipi send to finish */ + apic_wait_icr_idle(); - if (!(htic & HTIC_ColdR_Detect)) { - print_debug("Cold Reset.\r\n"); - } - if ((htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect)) { - print_debug("BIOS generated Reset.\r\n"); - } - if (htic & HTIC_INIT_Detect) { - print_debug("Init event.\r\n"); - } -#endif - cpu_init = (htic & HTIC_INIT_Detect); - if (cpu_init) { - print_debug("CPU INIT Detected.\r\n"); - } - return cpu_init; -} -/* -static void print_debug_pci_dev(unsigned dev) -{ - print_debug("PCI: "); - print_debug_hex8((dev >> 16) & 0xff); - print_debug_char(':'); - print_debug_hex8((dev >> 11) & 0x1f); - print_debug_char('.'); - print_debug_hex8((dev >> 8) & 7); -} - - -static void print_pci_devices(void) -{ - device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - print_debug_pci_dev(dev); - print_debug("\r\n"); + /* If I haven't halted spin forever */ + for(;;) { + hlt(); } } -*/ -/* -static void dump_pci_device(unsigned dev) -{ - int i; - print_debug_pci_dev(dev); - print_debug("\r\n"); - - for(i = 0; i <= 255; i++) { - unsigned char val; - if ((i & 0x0f) == 0) { - print_debug_hex8(i); - print_debug_char(':'); - } - val = pci_read_config8(dev, i); - print_debug_char(' '); - print_debug_hex8(val); - if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); - } - } -} -static void dump_pci_devices(void) -{ - device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - } -} - - - -static void dump_spd_registers(const struct mem_controller *ctrl) -{ - int i; - print_debug("\r\n"); - for(i = 0; i < 4; i++) { - unsigned device; - device = ctrl->channel0[i]; - if (device) { - int j; - print_debug("dimm: "); - print_debug_hex8(i); - print_debug(".0: "); - print_debug_hex8(device); - for(j = 0; j < 256; j++) { - int status; - unsigned char byte; - if ((j & 0xf) == 0) { - print_debug("\r\n"); - print_debug_hex8(j); - print_debug(": "); - } - status = smbus_read_byte(device, j); - if (status < 0) { - print_debug("bad device\r\n"); - - break; - } - byte = status & 0xff; - print_debug_hex8(byte); - print_debug_char(' '); - } - print_debug("\r\n"); - } - device = ctrl->channel1[i]; - if (device) { - int j; - print_debug("dimm: "); - print_debug_hex8(i); - print_debug(".1: "); - print_debug_hex8(device); - for(j = 0; j < 256; j++) { - int status; - unsigned char byte; - if ((j & 0xf) == 0) { - print_debug("\r\n"); - print_debug_hex8(j); - print_debug(": "); - } - status = smbus_read_byte(device, j); - - if (status < 0) { - print_debug("bad device\r\n"); - break; - } - byte = status & 0xff; - print_debug_hex8(byte); - print_debug_char(' '); - } - print_debug("\r\n"); - } - } -} - -*/ - - - +#define FIRST_CPU 1 +#define SECOND_CPU 1 +#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) static void main(void) { - static const struct mem_controller cpu0 = { - .f0 = PCI_DEV(0, 0x18, 0), - .f1 = PCI_DEV(0, 0x18, 1), - .f2 = PCI_DEV(0, 0x18, 2), - .f3 = PCI_DEV(0, 0x18, 3), - .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 }, - .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 }, - }; - static const struct mem_controller cpu1 = { - .f0 = PCI_DEV(0, 0x19, 0), - .f1 = PCI_DEV(0, 0x19, 1), - .f2 = PCI_DEV(0, 0x19, 2), - .f3 = PCI_DEV(0, 0x19, 3), - .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 }, - .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 }, - }; - - // device_t dev; - // unsigned where; - unsigned long reg; -// dev = PCI_ADDR(0, 0x19, 0, 0x6C) & ~0xff; -// where = PCI_ADDR(0, 0x19, 0, 0x6C) & 0xff; -#if 0 - init_apic_timer(); + /* + * GPIO28 of 8111 will control H0_MEMRESET_L + * GPIO29 of 8111 will control H1_MEMRESET_L + */ + static const struct mem_controller cpu[] = { +#if FIRST_CPU + { + .node_id = 0, + .f0 = PCI_DEV(0, 0x18, 0), + .f1 = PCI_DEV(0, 0x18, 1), + .f2 = PCI_DEV(0, 0x18, 2), + .f3 = PCI_DEV(0, 0x18, 3), + .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 }, + .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 }, + }, #endif - +#if SECOND_CPU + { + .node_id = 1, + .f0 = PCI_DEV(0, 0x19, 0), + .f1 = PCI_DEV(0, 0x19, 1), + .f2 = PCI_DEV(0, 0x19, 2), + .f3 = PCI_DEV(0, 0x19, 3), + .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 }, + .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 }, + }, +#endif + }; + if (cpu_init_detected()) { + asm("jmp __cpu_reset"); + } + enable_lapic(); + init_timer(); + if (!boot_cpu() ) { + notify_bsp_ap_is_stopped(); + stop_this_cpu(); + } uart_init(); console_init(); - if (boot_cpu() && !cpu_init_detected()) { - setup_default_resource_map(); - setup_coherent_ht_domain(); - enumerate_ht_chain(); -// print_pci_devices(); - enable_smbus(); -// sdram_initialize(); - // dump_spd_registers(&cpu0); - sdram_initialize(&cpu0); - // dump_spd_registers(&cpu1); -// sdram_initialize(&cpu1); - -// dump_pci_device(PCI_DEV(0, 0x18, 2)); -#if 0 - ram_fill( 0x00100000, 0x00180000); - ram_verify(0x00100000, 0x00180000); -#endif -//#ifdef MEMORY_1024MB -// ram_fill( 0x00000000, 0x00001000); -// ram_verify(0x00000000, 0x00001000); -//#endif -//#ifdef MEMROY_512MB -// ram_fill( 0x00000000, 0x01ffffff); -// ram_verify(0x00000000, 0x01ffffff); -//#endif - /* Check the first 512M */ -/* msr_t msr; - msr = rdmsr(TOP_MEM); - print_debug("TOP_MEM: "); - print_debug_hex32(msr.hi); - print_debug_hex32(msr.lo); - print_debug("\r\n"); - ram_check(0x00000000, msr.lo); - */ -/* - reg = *((volatile unsigned long *)(APIC_DEFAULT_BASE+APIC_ID)); - print_debug("bootstrap cpu apic_id: "); - print_debug_hex32(reg>>24); - print_debug("\r\n"); -*/ - - // Start AP now - reg = pci_read_config32(PCI_DEV(0, 0x19, 0), 0x6C); - reg &= 0xffffff8c; - reg |= 0x00000070; - pci_write_config32(PCI_DEV(0, 0x19, 0), 0x6C, reg); //start AP - for(;;) { - reg = pci_read_config32(PCI_DEV(0, 0x19, 0), 0x6C); - if((reg & (1<<4))==0) break; // wait until AP stop - } - reg |= 1<<4; - pci_write_config32(PCI_DEV(0, 0x19, 0), 0x6C, reg); - - } - else { - // Need to init second cpu's APIC id - // It's AP - -// apic_write(APIC_ID,(1<<24)); - reg = *((volatile unsigned long *)(APIC_DEFAULT_BASE+APIC_ID)); -/* print_debug("applicaton cpu apic_id: "); - print_debug_hex32(reg>>24); - print_debug("\r\n"); - if((reg>>24)==7){ // FIXME: Need to read NodeID at first. - *((volatile unsigned long *)(APIC_DEFAULT_BASE+APIC_ID))=1<<24; - }*/ - if((reg>>24)!=0) { -// before hlt clear the ColdResetbit - - //notify BSP that AP is stopped - reg = pci_read_config32(PCI_DEV(0, 0x19, 0), 0x6C); - reg &= ~(1<<4); - pci_write_config32(PCI_DEV(0, 0x19, 0), 0x6C, reg); - - asm("hlt"); - } - - - } + setup_default_resource_map(); + setup_coherent_ht_domain(); + enumerate_ht_chain(0); + distinguish_cpu_resets(0); +#if 0 + print_pci_devices(); +#endif + enable_smbus(); +#if 0 + dump_spd_registers(&cpu[0]); +#endif + memreset_setup(); + sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + +#if 0 + dump_pci_devices(); +#endif +#if 0 + dump_pci_device(PCI_DEV(0, 0x18, 2)); +#endif + + /* Check all of memory */ +#if 0 + msr_t msr; + msr = rdmsr(TOP_MEM); + print_debug("TOP_MEM: "); + print_debug_hex32(msr.hi); + print_debug_hex32(msr.lo); + print_debug("\r\n"); +#endif +/* +#if 1 + ram_check(0x00000000, msr.lo); +#else +#if TOTAL_CPUS < 2 + // Check 16MB of memory @ 0 + ram_check(0x00000000, 0x01000000); +#else + // Check 16MB of memory @ 2GB + ram_check(0x80000000, 0x81000000); +#endif +#endif +*/ } diff --git a/src/mainboard/tyan/s2880/failover.c b/src/mainboard/tyan/s2880/failover.c index cda8ea8076..8eeeaef7e1 100644 --- a/src/mainboard/tyan/s2880/failover.c +++ b/src/mainboard/tyan/s2880/failover.c @@ -2,25 +2,37 @@ #include #include #include +#include #include "arch/romcc_io.h" #include "pc80/mc146818rtc_early.c" #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" - - +#include "cpu/p6/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" static void main(void) { - if (do_normal_boot()) { - /* Nothing special needs to be done to find bus 0 */ + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(0); - /* Allow the HT devices to be found */ - enumerate_ht_chain(); + /* Setup the 8111 */ + amd8111_enable_rom(); - /* Setup the 8111 */ - amd8111_enable_rom(); - - /* Jump to the normal image */ + /* Is this a cpu reset? */ + if (cpu_init_detected()) { + if (last_boot_normal()) { + asm("jmp __normal_image"); + } else { + asm("jmp __cpu_reset"); + } + } + /* Is this a secondary cpu? */ + else if (!boot_cpu() && last_boot_normal()) { + asm("jmp __normal_image"); + } + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { asm("jmp __normal_image"); } } diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 6828294ead..8bf8d15dd9 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -77,6 +77,41 @@ static void disable_probes(void) print_debug("done.\r\n"); } +//BY LYH +#define WAIT_TIMES 1000 +static void wait_ap_stop(u8 node) +{ + unsigned long reg; + unsigned long i; + for(i=0;i>= 24; +/* print_debug("applicaton cpu apic_id: "); + print_debug_hex32(apic_id); + print_debug("\r\n"); + }*/ + if(apic_id!=0) { //AP apic_id == node_id ?? +// set the ColdResetbit to notify BSP that AP is stopped + reg = pci_read_config32(NODE_HT(apic_id), 0x6C); + reg |= 1<<4; + pci_write_config32(NODE_HT(apic_id), 0x6C, reg); + } + +} +//BY LYH END static void enable_routing(u8 node) { @@ -109,8 +144,15 @@ static void enable_routing(u8 node) print_debug_hex32(node); val=pci_read_config32(NODE_HT(node), 0x6c); - val &= ~((1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0)); - pci_write_config32(NODE_HT(node), 0x6c, val); + val &= ~((1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0)); + pci_write_config32(NODE_HT(node), 0x6c, val); +//BY LYH +#if 1 + if(node!=0) { + wait_ap_stop(node); + } +#endif +//BY LYH END print_debug(" done.\r\n"); } @@ -285,9 +327,9 @@ static u8 setup_smp(void) /* We found 2 nodes so far */ setup_node(0, cpus); /* Node 1 is there. Setup Node 0 correctly */ setup_remote_node(1, cpus); /* Setup the routes on the remote node */ - rename_temp_node(1); /* Rename Node 7 to Node 1 */ - enable_routing(1); /* Enable routing on Node 1 */ - + rename_temp_node(1); /* Rename Node 7 to Node 1 */ + enable_routing(1); /* Enable routing on Node 1 */ + clear_temp_row(0); /* delete temporary connection */ #if MAX_CPUS > 2 @@ -323,14 +365,14 @@ static u8 setup_smp(void) setup_temp_row(0,2,cpus); setup_temp_node(2,cpus); - rename_temp_node(2); - enable_routing(2); - + rename_temp_node(2); + enable_routing(2); + setup_temp_row(0,1,cpus); setup_temp_row(1,3,cpus); setup_temp_node(3,cpus); - rename_temp_node(3); - enable_routing(3); /* enable routing on node 3 (temp.) */ + rename_temp_node(3); + enable_routing(3); /* enable routing on node 3 (temp.) */ clear_temp_row(0); clear_temp_row(1); @@ -394,6 +436,42 @@ static unsigned int cpuid(unsigned int op) static void coherent_ht_finalize(unsigned cpus) { +//BY LYH +#if 1 + static const unsigned int register_values[] = { + PCI_ADDR(0, 0x18, 0, 0x84), 0x88ff9c05, 0x11000020, + PCI_ADDR(0, 0x18, 0, 0xa4), 0x88ff9c05, 0x11000020, + PCI_ADDR(0, 0x18, 0, 0xc4), 0x88ff9c05, 0x770000d0, + PCI_ADDR(0, 0x19, 0, 0x84), 0x88ff9c05, 0x770000d0, + PCI_ADDR(0, 0x19, 0, 0xa4), 0x88ff9c05, 0x11000020, + PCI_ADDR(0, 0x19, 0, 0xc4), 0x88ff9c05, 0x770000d0, + + + PCI_ADDR(0, 0x18, 0, 0x88), 0xfffff0ff, 0x00000400, + PCI_ADDR(0, 0x18, 0, 0xa8), 0xfffff0ff, 0x00000500, + PCI_ADDR(0, 0x18, 0, 0xc8), 0xfffff0ff, 0x00000000, + PCI_ADDR(0, 0x19, 0, 0x88), 0xfffff0ff, 0x00000000, + PCI_ADDR(0, 0x19, 0, 0xa8), 0xfffff0ff, 0x00000500, + PCI_ADDR(0, 0x19, 0, 0xc8), 0xfffff0ff, 0x00000000, + + PCI_ADDR(0, 0x18, 0, 0x94), 0xff0000ff, 0x00ff0000, + PCI_ADDR(0, 0x18, 0, 0xb4), 0xff0000ff, 0x00000000, + PCI_ADDR(0, 0x18, 0, 0xd4), 0xff0000ff, 0x00000000, + PCI_ADDR(0, 0x19, 0, 0x94), 0xff0000ff, 0x00000000, + PCI_ADDR(0, 0x19, 0, 0xb4), 0xff0000ff, 0x00000000, + PCI_ADDR(0, 0x19, 0, 0xd4), 0xff0000ff, 0x00000000, + + }; + int i; + int max; + + + device_t dev; + unsigned where; + unsigned long reg; +#endif +//BY LYH END + int node; bool rev_a0; @@ -416,7 +494,7 @@ static void coherent_ht_finalize(unsigned cpus) pci_write_config32(NODE_HT(node),0x60,val); val=pci_read_config32(NODE_HT(node), 0x68); - val |= 0x00008000; + val |= 0x0f00c800; // 0x00008000->0f00c800 BY LYH pci_write_config32(NODE_HT(node),0x68,val); if (rev_a0) { @@ -425,6 +503,28 @@ static void coherent_ht_finalize(unsigned cpus) pci_write_config32(NODE_HT(node),0xd4,0); } } +//BY LYH +#if 1 + print_debug("setting up coherent ht domain....\r\n"); + max = sizeof(register_values)/sizeof(register_values[0]); + for(i = 0; i < max; i += 3) { +#if 0 + print_debug_hex32(i); + print_debug(": "); + print_debug_hex32(register_values[i]); + print_debug(" <-"); + print_debug_hex32(register_values[i+2]); + print_debug("\r\n"); +#endif + dev = register_values[i] & ~0xff; + where = register_values[i] & 0xff; + reg = pci_read_config32(dev, where); + reg &= register_values[i+1]; + reg |= register_values[i+2]; + pci_write_config32(dev, where, reg); + } +#endif +//BY LYH END #if 1 print_debug("done\r\n"); diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 1b258c62ce..6659641a1f 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -1249,7 +1249,14 @@ static void order_dimms(const struct mem_controller *ctrl) tom |= (1 << (canidate + 24)); /* Recompute the cs base register value */ - csbase = (tom << 21) | 1; +#if 1 // BY LYH Need to count from 0 for every memory controller + csbase = ((tom - (base_k>>15))<< 21) | 1; + print_debug("csbase="); + print_debug_hex32(csbase); + print_debug("\r\n"); +#else //BY LYH END + csbase = (tom << 21) | 1; +#endif /* Increment the top of memory */ tom += size; @@ -1276,6 +1283,14 @@ static void order_dimms(const struct mem_controller *ctrl) print_debug("\r\n"); #endif route_dram_accesses(ctrl, base_k, tom_k); + +#if 0 //BY LYH + if(ctrl->node_id==1) { + pci_write_config32(ctrl->f2, DRAM_CSBASE, 0x00000001); + + } +#endif + set_top_mem(tom_k); } @@ -2224,12 +2239,12 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug_hex32(dcl); print_debug("\r\n"); #endif -#if 1 +#if 0 dcl &= ~DCL_DimmEccEn; #endif #warning "FIXME set the ECC type to perform" #warning "FIXME initialize the scrub registers" -#if 0 +#if 1 if (dcl & DCL_DimmEccEn) { print_debug("ECC enabled\r\n"); } @@ -2260,7 +2275,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) } else { print_debug(" done\r\n"); } -#if 0 +#if 1 if (dcl & DCL_DimmEccEn) { print_debug("Clearing memory: "); loops = 0; diff --git a/src/southbridge/amd/amd8111/Config.lb b/src/southbridge/amd/amd8111/Config.lb index ef8734a275..f8f38a9964 100644 --- a/src/southbridge/amd/amd8111/Config.lb +++ b/src/southbridge/amd/amd8111/Config.lb @@ -2,3 +2,4 @@ driver amd8111_usb.o driver amd8111_lpc.o driver amd8111_ide.o driver amd8111_acpi.o +driver amd8111_usb2.o diff --git a/src/southbridge/amd/amd8131/amd8131_bridge.c b/src/southbridge/amd/amd8131/amd8131_bridge.c index ded5480234..ba90cad974 100644 --- a/src/southbridge/amd/amd8131/amd8131_bridge.c +++ b/src/southbridge/amd/amd8131/amd8131_bridge.c @@ -12,12 +12,11 @@ static void pcix_init(device_t dev) uint16_t word; uint8_t byte; - /* Enable memory write and invalidate ??? */ byte = pci_read_config8(dev, 0x04); byte |= 0x10; pci_write_config8(dev, 0x04, byte); - + /* Set drive strength */ word = pci_read_config16(dev, 0xe0); word = 0x0404; @@ -30,7 +29,7 @@ static void pcix_init(device_t dev) word = pci_read_config16(dev, 0xe8); word = 0x0404; pci_write_config16(dev, 0xe8, word); - + return; } @@ -58,6 +57,14 @@ static void ioapic_enable(device_t dev) value &= ~((1 << 1) | (1 << 0)); } pci_write_config32(dev, 0x44, value); + +//BY LYH + value = pci_read_config32(dev, 0x4); + value |= 6; + pci_write_config32(dev, 0x4, value); +//BY LYH END + + } static struct device_operations ioapic_ops = {