intel/sch: Switch to MMCONF_SUPPORT_DEFAULT

Untested, only affected board is iwave/iwRainbowG6.

Change-Id: Ie3c40ede85c9f89b54804dd2a411645be93911bf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17528
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2013-10-27 13:35:54 +02:00
parent bac0fad408
commit ebc21d125f
3 changed files with 42 additions and 3 deletions

View File

@ -25,6 +25,10 @@ config SOC_INTEL_SCH
if SOC_INTEL_SCH
config BOOTBLOCK_NORTHBRIDGE_INIT
string
default "soc/intel/sch/bootblock.c"
config VGA_BIOS_ID
string
default "8086,8108"

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@ -0,0 +1,38 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
/* Copy the bare minimum from port_access.c to enable MMCONF. */
#define MSG_OPCODE_READ 0xD0000000
#define MSG_OPCODE_WRITE 0xE0000000
#define MCR 0xD0
#define MDR 0xD4
static void sch_port_access_write(int port, int reg, int bytes, long data)
{
pci_io_write_config32(PCI_DEV(0, 0, 0), MDR, data);
pci_io_write_config32(PCI_DEV(0, 0, 0), MCR,
(MSG_OPCODE_WRITE | (port << 16) | (reg << 8)));
pci_io_read_config32(PCI_DEV(0, 0, 0), MDR);
}
static void bootblock_northbridge_init(void)
{
/* Enable PCI MMCONF decoding BAR. */
sch_port_access_write(0, 0, 4, DEFAULT_PCIEXBAR | 1); /* pre-b1 */
sch_port_access_write(2, 9, 4, DEFAULT_PCIEXBAR | 1); /* b1+ */
}

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@ -196,9 +196,6 @@ static void sch_setup_non_standard_bars(void)
/* Base of Stolen Memory Address 0x1080 size 64B */
pci_write_config32(PCI_DEV(0, 0x02, 0), 0x5C, 0x3F800000);
sch_port_access_write(0, 0, 4, DEFAULT_PCIEXBAR | 1); /* pre-b1 */
sch_port_access_write(2, 9, 4, DEFAULT_PCIEXBAR | 1); /* b1+ */
/* RCBA */
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xF0,
((uintptr_t)DEFAULT_RCBABASE | 1));