intel/sch: Switch to MMCONF_SUPPORT_DEFAULT
Untested, only affected board is iwave/iwRainbowG6. Change-Id: Ie3c40ede85c9f89b54804dd2a411645be93911bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17528 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -25,6 +25,10 @@ config SOC_INTEL_SCH
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if SOC_INTEL_SCH
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config BOOTBLOCK_NORTHBRIDGE_INIT
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string
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default "soc/intel/sch/bootblock.c"
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config VGA_BIOS_ID
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string
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default "8086,8108"
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@ -0,0 +1,38 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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/* Copy the bare minimum from port_access.c to enable MMCONF. */
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#define MSG_OPCODE_READ 0xD0000000
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#define MSG_OPCODE_WRITE 0xE0000000
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#define MCR 0xD0
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#define MDR 0xD4
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static void sch_port_access_write(int port, int reg, int bytes, long data)
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{
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pci_io_write_config32(PCI_DEV(0, 0, 0), MDR, data);
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pci_io_write_config32(PCI_DEV(0, 0, 0), MCR,
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(MSG_OPCODE_WRITE | (port << 16) | (reg << 8)));
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pci_io_read_config32(PCI_DEV(0, 0, 0), MDR);
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}
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static void bootblock_northbridge_init(void)
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{
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/* Enable PCI MMCONF decoding BAR. */
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sch_port_access_write(0, 0, 4, DEFAULT_PCIEXBAR | 1); /* pre-b1 */
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sch_port_access_write(2, 9, 4, DEFAULT_PCIEXBAR | 1); /* b1+ */
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}
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@ -196,9 +196,6 @@ static void sch_setup_non_standard_bars(void)
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/* Base of Stolen Memory Address 0x1080 size 64B */
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pci_write_config32(PCI_DEV(0, 0x02, 0), 0x5C, 0x3F800000);
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sch_port_access_write(0, 0, 4, DEFAULT_PCIEXBAR | 1); /* pre-b1 */
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sch_port_access_write(2, 9, 4, DEFAULT_PCIEXBAR | 1); /* b1+ */
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/* RCBA */
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xF0,
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((uintptr_t)DEFAULT_RCBABASE | 1));
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