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Revert "soc/intel/{tigerlake,meteorlake}: Check ITBT FW version" 

This reverts commit 2e10a6d6f3.

Reason for revert: The FW version check is not supported except
for ADL platform. Reverted change broke S0ix functionality;
the original CL was added as HW W/A for ADL ONLY.

BUG=b:306214725
TEST=S0ix cycles on Rex with TBT Device attached.
Change-Id: Ib8eb11d36eac4e1c94a3349386442fa3eeeaef37
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78457
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ravi Sarawadi 2023-10-26 13:25:35 -07:00 committed by Subrata Banik
parent f89bb82832
commit ebd4c3d113
4 changed files with 2 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/soc/intel/meteorlake/acpi/tcss.asl
View File

@ -452,10 +452,6 @@ Scope (\_SB.PCI0)
/* DMA0 is not in D3Cold now. */
\_SB.PCI0.TDM0.D3CE() /* Enable DMA RTD3 */
If (\_SB.PCI0.TDM0.IF30 != 1) {
Return
}
Printf("Push TBT RPs to D3Cold together")
If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) {
/* Put RP0 to D3 cold. */
@ -511,10 +507,6 @@ Scope (\_SB.PCI0)
/* DMA1 is not in D3Cold now */
\_SB.PCI0.TDM1.D3CE() /* Enable DMA RTD3. */
If (\_SB.PCI0.TDM1.IF30 != 1) {
Return
}
Printf("Push TBT RPs to D3Cold together")
If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) {
/* Put RP2 to D3 cold. */

3
src/soc/intel/meteorlake/acpi/tcss_dma.asl
View File

@ -11,8 +11,7 @@ Field (DPME, AnyAcc, NoLock, Preserve)
, 6,
PMES, 1, /* 15, PME_STATUS */
Offset(0xC8), /* 0xC8, TBT NVM FW Revision */
, 30,
IF30, 1, /* ITBT FW Version Bit30 */
, 31,
INFR, 1, /* TBT NVM FW Ready */
Offset(0xEC), /* 0xEC, TBT TO PCIE Register */
TB2P, 32, /* TBT to PCIe */

8
src/soc/intel/tigerlake/acpi/tcss.asl
View File

@ -567,10 +567,6 @@ Scope (\_SB.PCI0)
/* DMA0 is not in D3Cold now. */
\_SB.PCI0.TDM0.D3CE() /* Enable DMA RTD3 */
If (\_SB.PCI0.TDM0.IF30 != 1) {
Return
}
Printf("Push TBT RPs to D3Cold together")
If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) {
/* Put RP0 to D3 cold. */
@ -626,10 +622,6 @@ Scope (\_SB.PCI0)
/* DMA1 is not in D3Cold now */
\_SB.PCI0.TDM1.D3CE() /* Enable DMA RTD3. */
If (\_SB.PCI0.TDM1.IF30 != 1) {
Return
}
Printf("Push TBT RPs to D3Cold together")
If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) {
/* Put RP2 to D3 cold. */

3
src/soc/intel/tigerlake/acpi/tcss_dma.asl
View File

@ -11,8 +11,7 @@ Field (DPME, AnyAcc, NoLock, Preserve)
, 6,
PMES, 1, /* 15, PME_STATUS */
Offset(0xC8), /* 0xC8, TBT NVM FW Revision */
, 30,
IF30, 1, /* ITBT FW Version Bit30 */
, 31,
INFR, 1, /* TBT NVM FW Ready */
Offset(0xEC), /* 0xEC, TBT TO PCIE Register */
TB2P, 32, /* TBT to PCIe */