mb/gigabyte: Add GA-D510UD
Booted fine on the first try. Most things work properly, but I haven't tested them thoroughly. Native raminit chokes with a DIMM in the second slot, but the first slot works properly. Change-Id: I2126c7d31e0d8a8f80df69fdcdcd202b87f219a4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons
Patrick Georgi
parent
27545df163
commit
ebd4dfa53e
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@ -0,0 +1,27 @@
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## SPDX-License-Identifier: GPL-2.0-only
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if BOARD_GIGABYTE_GA_D510UD
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_512
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select CPU_INTEL_SOCKET_FCBGA559
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_CMOS_DEFAULT
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select HAVE_OPTION_TABLE
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select INTEL_GMA_HAVE_VBT
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select NORTHBRIDGE_INTEL_PINEVIEW
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select REALTEK_8168_RESET
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select SOUTHBRIDGE_INTEL_I82801GX
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select SUPERIO_ITE_IT8720F
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config MAINBOARD_DIR
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string
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default "gigabyte/ga-d510ud"
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config MAINBOARD_PART_NUMBER
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string
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default "GA-D510UD"
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endif # BOARD_GIGABYTE_GA_D510UD
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@ -0,0 +1,2 @@
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config BOARD_GIGABYTE_GA_D510UD
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bool "GA-D510UD"
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@ -0,0 +1,8 @@
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## SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += early_init.c
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romstage-y += early_init.c
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romstage-y += gpio.c
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ramstage-y += cstates.c
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@ -0,0 +1,21 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* This is the IRQ routing for the 0:1e.0 PCI bridge of the NM10 */
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If (PICM) {
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Return (Package() {
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Package() { 0x0000ffff, 0, 0, 0x15},
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Package() { 0x0000ffff, 1, 0, 0x16},
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Package() { 0x0000ffff, 2, 0, 0x17},
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Package() { 0x0000ffff, 3, 0, 0x14},
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Package() { 0x0001ffff, 0, 0, 0x13},
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})
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} Else {
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Return (Package() {
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Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
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Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
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Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
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Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
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Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKD, 0},
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})
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}
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/* SPDX-License-Identifier: GPL-2.0-only */
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#undef SUPERIO_DEV
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#undef SUPERIO_PNP_BASE
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#undef IT8720F_SHOW_SP1
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#undef IT8720F_SHOW_SP2
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#undef IT8720F_SHOW_EC
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#undef IT8720F_SHOW_KBCK
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#undef IT8720F_SHOW_KBCM
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#define SUPERIO_DEV SIO0
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#define SUPERIO_PNP_BASE 0x2e
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#define IT8720F_SHOW_SP1
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#define IT8720F_SHOW_SP2
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#define IT8720F_SHOW_EC
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#define IT8720F_SHOW_KBCK
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#define IT8720F_SHOW_KBCM
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#include <superio/ite/it8720f/acpi/superio.asl>
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@ -0,0 +1,6 @@
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Category: mini
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Board URL: https://www.gigabyte.com/Motherboard/GA-D510UD-rev-10
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ROM package: SOIC-8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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@ -0,0 +1,5 @@
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boot_option=Fallback
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debug_level=Debug
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power_on_after_fail=Disable
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nmi=Enable
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gfx_uma_size=8M
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## SPDX-License-Identifier: GPL-2.0-only
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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388 4 h 0 reboot_counter
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# -----------------------------------------------------------------
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# coreboot config options: console
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395 4 e 6 debug_level
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# coreboot config options: southbridge
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408 1 e 1 nmi
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409 2 e 7 power_on_after_fail
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# coreboot config options: bootloader
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416 512 s 0 boot_devices
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# coreboot config options: cpu
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# coreboot config options: northbridge
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952 3 e 11 gfx_uma_size
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# coreboot config options: check sums
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984 16 h 0 check_sum
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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6 0 Emergency
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6 1 Alert
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6 2 Critical
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6 3 Error
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6 4 Warning
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6 5 Notice
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6 6 Info
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6 7 Debug
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6 8 Spew
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7 0 Disable
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7 1 Enable
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7 2 Keep
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11 0 8M
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11 1 16M
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11 2 32M
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11 3 48M
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11 4 64M
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11 5 128M
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11 6 256M
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# -----------------------------------------------------------------
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checksums
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checksum 392 983 984
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@ -0,0 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpigen.h>
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int get_cst_entries(acpi_cstate_t **entries)
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{
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return 0;
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}
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Binary file not shown.
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## SPDX-License-Identifier: GPL-2.0-only
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chip northbridge/intel/pineview
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register "use_crt" = "1"
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device cpu_cluster 0 on
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chip cpu/intel/socket_FCBGA559
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device lapic 0 on end
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end
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end
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device domain 0 on
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subsystemid 0x105b 0x0d55 inherit
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device pci 0.0 on end # Host Bridge
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device pci 2.0 on end # iGPU
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device pci 2.1 off end # iGPU 2
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chip southbridge/intel/i82801gx
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register "pirqa_routing" = "0x0b"
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register "pirqb_routing" = "0x0b"
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register "pirqc_routing" = "0x0b"
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register "pirqd_routing" = "0x0b"
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register "pirqe_routing" = "0x0b"
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register "pirqf_routing" = "0x0b"
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register "pirqg_routing" = "0x0b"
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register "pirqh_routing" = "0x0b"
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register "sata_ports_implemented" = "0x3"
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register "gpe0_en" = "0x441"
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register "gen1_dec" = "0x00040291" # Environment Controller
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device pci 1b.0 on end # HD Audio
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device pci 1c.0 on end # PCIe 1: Realtek GbE NIC
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device pci 1c.1 on end # PCIe 2: JMB363 SATA/IDE
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device pci 1c.2 off end # PCIe 3
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device pci 1c.3 off end # PCIe 4
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device pci 1d.0 on end # UHCI
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device pci 1d.1 on end # UHCI
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device pci 1d.2 on end # UHCI
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device pci 1d.3 on end # UHCI
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device pci 1d.7 on end # EHCI
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device pci 1e.0 on end # PCI bridge
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device pci 1f.0 on # LPC bridge
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chip superio/ite/it8720f
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device pnp 2e.0 off end # Floppy
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device pnp 2e.1 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.2 on # COM2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.3 on # PP
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io 0x60 = 0x378
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io 0x62 = 0
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irq 0x70 = 7
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end
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device pnp 2e.4 on # EC
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io 0x60 = 0x0290
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io 0x62 = 0
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irq 0x70 = 0
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end
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device pnp 2e.5 on # PS/2 keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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end
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device pnp 2e.6 on # PS/2 mouse
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irq 0x70 = 12
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end
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device pnp 2e.7 off end # GPIO
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device pnp 2e.a off end # CIR
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end
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end
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device pci 1f.2 on end # SATA
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device pci 1f.3 on end # SMbus
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end
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end
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end
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20090419
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)
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{
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#include <acpi/dsdt_top.asl>
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#include <southbridge/intel/common/acpi/platform.asl>
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#include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
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#include <cpu/intel/speedstep/acpi/cpu.asl>
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Device (\_SB.PCI0)
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{
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#include <northbridge/intel/pineview/acpi/pineview.asl>
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#include <southbridge/intel/i82801gx/acpi/ich7.asl>
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}
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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}
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <console/console.h>
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#include <device/pnp_ops.h>
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#include <northbridge/intel/pineview/pineview.h>
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#include <southbridge/intel/i82801gx/i82801gx.h>
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#include <superio/ite/common/ite.h>
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#include <superio/ite/it8720f/it8720f.h>
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#define SERIAL_DEV PNP_DEV(0x2e, IT8720F_SP1)
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#define GPIO_DEV PNP_DEV(0x2e, IT8720F_GPIO)
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#define EC_DEV PNP_DEV(0x2e, IT8720F_EC)
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void bootblock_mainboard_early_init(void)
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{
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/* Set default GPIOs on superio */
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pnp_enter_conf_state(GPIO_DEV);
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pnp_set_logical_device(GPIO_DEV);
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pnp_write_config(GPIO_DEV, 0x25, 0x00);
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pnp_write_config(GPIO_DEV, 0x26, 0x0c);
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pnp_write_config(GPIO_DEV, 0x28, 0x41);
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pnp_write_config(GPIO_DEV, 0x2c, 0x01);
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pnp_write_config(GPIO_DEV, 0x62, 0x08);
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pnp_write_config(GPIO_DEV, 0x72, 0x00);
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pnp_write_config(GPIO_DEV, 0xb8, 0x00);
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pnp_write_config(GPIO_DEV, 0xc0, 0x00);
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pnp_write_config(GPIO_DEV, 0xc1, 0x0c);
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pnp_write_config(GPIO_DEV, 0xc3, 0x41);
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pnp_write_config(GPIO_DEV, 0xc8, 0x00);
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pnp_write_config(GPIO_DEV, 0xcb, 0x00);
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pnp_write_config(GPIO_DEV, 0xe9, 0x01);
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pnp_write_config(GPIO_DEV, 0xfc, 0xa4);
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pnp_exit_conf_state(GPIO_DEV);
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ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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pnp_enter_conf_state(GPIO_DEV);
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pnp_set_logical_device(GPIO_DEV);
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printk(BIOS_DEBUG, "ITE register 0xef: 0x%02x ", pnp_read_config(GPIO_DEV, 0xef));
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/* Disable SIO reboot */
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pnp_write_config(GPIO_DEV, 0xef, 0x7e);
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printk(BIOS_DEBUG, "=> 0x%02x\n", pnp_read_config(GPIO_DEV, 0xef));
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pnp_set_logical_device(EC_DEV);
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pnp_write_config(EC_DEV, 0x70, 0x00); /* Don't use IRQ9 */
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pnp_write_config(EC_DEV, 0x30, 0x01); /* Enable */
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pnp_exit_conf_state(GPIO_DEV);
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}
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void get_mb_spd_addrmap(u8 *spd_addrmap)
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{
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spd_addrmap[0] = 0x50;
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spd_addrmap[1] = 0x51;
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}
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@ -0,0 +1,113 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <southbridge/intel/common/gpio.h>
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static const struct pch_gpio_set1 pch_gpio_set1_mode = {
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.gpio0 = GPIO_MODE_NATIVE,
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.gpio1 = GPIO_MODE_NATIVE,
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.gpio2 = GPIO_MODE_NATIVE,
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.gpio3 = GPIO_MODE_NATIVE,
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.gpio4 = GPIO_MODE_NATIVE,
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.gpio5 = GPIO_MODE_NATIVE,
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.gpio6 = GPIO_MODE_GPIO,
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.gpio7 = GPIO_MODE_GPIO,
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.gpio8 = GPIO_MODE_GPIO,
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.gpio9 = GPIO_MODE_GPIO,
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.gpio10 = GPIO_MODE_GPIO,
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.gpio11 = GPIO_MODE_GPIO,
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.gpio12 = GPIO_MODE_GPIO,
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.gpio13 = GPIO_MODE_GPIO,
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.gpio14 = GPIO_MODE_GPIO,
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.gpio15 = GPIO_MODE_GPIO,
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.gpio16 = GPIO_MODE_NATIVE,
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.gpio17 = GPIO_MODE_NATIVE,
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.gpio18 = GPIO_MODE_NATIVE,
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.gpio19 = GPIO_MODE_NATIVE,
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.gpio20 = GPIO_MODE_GPIO,
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.gpio21 = GPIO_MODE_NATIVE,
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.gpio22 = GPIO_MODE_NATIVE,
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.gpio23 = GPIO_MODE_NATIVE,
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.gpio24 = GPIO_MODE_GPIO,
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.gpio25 = GPIO_MODE_GPIO,
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.gpio26 = GPIO_MODE_GPIO,
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.gpio27 = GPIO_MODE_GPIO,
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.gpio28 = GPIO_MODE_GPIO,
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.gpio29 = GPIO_MODE_NATIVE,
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.gpio30 = GPIO_MODE_NATIVE,
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.gpio31 = GPIO_MODE_NATIVE,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_direction = {
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.gpio6 = GPIO_DIR_INPUT,
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.gpio7 = GPIO_DIR_INPUT,
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.gpio8 = GPIO_DIR_INPUT,
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.gpio9 = GPIO_DIR_INPUT,
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.gpio10 = GPIO_DIR_INPUT,
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.gpio11 = GPIO_DIR_INPUT,
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.gpio12 = GPIO_DIR_INPUT,
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.gpio13 = GPIO_DIR_INPUT,
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.gpio14 = GPIO_DIR_INPUT,
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.gpio15 = GPIO_DIR_INPUT,
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.gpio20 = GPIO_DIR_OUTPUT,
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.gpio24 = GPIO_DIR_OUTPUT,
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.gpio25 = GPIO_DIR_INPUT,
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.gpio26 = GPIO_DIR_OUTPUT,
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.gpio27 = GPIO_DIR_OUTPUT,
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.gpio28 = GPIO_DIR_OUTPUT,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_level = {
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.gpio20 = GPIO_LEVEL_HIGH,
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.gpio24 = GPIO_LEVEL_LOW,
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.gpio26 = GPIO_LEVEL_LOW,
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.gpio27 = GPIO_LEVEL_LOW,
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.gpio28 = GPIO_LEVEL_LOW,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_invert = {
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.gpio6 = GPIO_INVERT,
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.gpio7 = GPIO_INVERT,
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.gpio8 = GPIO_INVERT,
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.gpio11 = GPIO_INVERT,
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.gpio12 = GPIO_INVERT,
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.gpio13 = GPIO_INVERT,
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};
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static const struct pch_gpio_set2 pch_gpio_set2_mode = {
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.gpio32 = GPIO_MODE_NATIVE,
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.gpio33 = GPIO_MODE_GPIO,
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.gpio34 = GPIO_MODE_GPIO,
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.gpio35 = GPIO_MODE_NATIVE,
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.gpio36 = GPIO_MODE_NATIVE,
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.gpio37 = GPIO_MODE_NATIVE,
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.gpio38 = GPIO_MODE_GPIO,
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.gpio39 = GPIO_MODE_GPIO,
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};
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static const struct pch_gpio_set2 pch_gpio_set2_direction = {
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.gpio33 = GPIO_DIR_OUTPUT,
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.gpio34 = GPIO_DIR_OUTPUT,
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.gpio38 = GPIO_DIR_INPUT,
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.gpio39 = GPIO_DIR_INPUT,
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};
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static const struct pch_gpio_set2 pch_gpio_set2_level = {
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.gpio33 = GPIO_LEVEL_HIGH,
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||||
.gpio34 = GPIO_LEVEL_LOW,
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||||
.gpio38 = GPIO_LEVEL_HIGH,
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||||
.gpio39 = GPIO_LEVEL_HIGH,
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};
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||||
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const struct pch_gpio_map mainboard_gpio_map = {
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||||
.set1 = {
|
||||
.mode = &pch_gpio_set1_mode,
|
||||
.direction = &pch_gpio_set1_direction,
|
||||
.level = &pch_gpio_set1_level,
|
||||
.invert = &pch_gpio_set1_invert,
|
||||
},
|
||||
.set2 = {
|
||||
.mode = &pch_gpio_set2_mode,
|
||||
.direction = &pch_gpio_set2_direction,
|
||||
.level = &pch_gpio_set2_level,
|
||||
},
|
||||
};
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* coreboot specific header */
|
||||
0x10ec0662,
|
||||
0x105b0d55, /* Subsystem ID */
|
||||
10, /* Number of entries */
|
||||
|
||||
/* Pin Widget Verb Table */
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x01014c10),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x01a19c30),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x02a19c31),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x0181343f),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x02214c1f),
|
||||
AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x4005c603),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x99430120),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
Loading…
Reference in New Issue