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mb/google/brya/var/banshee: Update the GPP_D12 as USB_C3_LSX_RX 

Update the GPP_D12 according to USB_C3_LSX_RX.

BUG=b:225081954
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
The device can be recognized when it is attached in port3.
localhost /sys/bus/thunderbolt/devices # ls
0-0  1-0  1-0:3.1  1-3  domain0  domain1

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I38caa76c855e683eb0587eb67ee9abc91af4545d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Frank Wu 2022-03-29 18:26:28 +08:00 committed by Tim Wawrzynczak
parent 1c27671504
commit ebd6dec110
1 changed files with 2 additions and 1 deletions
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3
src/mainboard/google/brya/variants/banshee/gpio.c
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@ -101,7 +101,8 @@ static const struct pad_config override_gpio_table[] = {
/* D10 : ISH_SPI_CLK ==> USB_C2_LSX_RX_STRAP */ /* D10 : ISH_SPI_CLK ==> USB_C2_LSX_RX_STRAP */
/* D11 : ISH_SPI_MISO ==> USB_C3_LSX_TX */ /* D11 : ISH_SPI_MISO ==> USB_C3_LSX_TX */
PAD_CFG_NF_LOCK(GPP_D11, NONE, NF4, LOCK_CONFIG), PAD_CFG_NF_LOCK(GPP_D11, NONE, NF4, LOCK_CONFIG),
/* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */ /* D12 : ISH_SPI_MOSI ==> USB_C3_LSX_RX */
PAD_CFG_NF_LOCK(GPP_D12, NONE, NF4, LOCK_CONFIG),
/* D13 : ISH_UART0_RXD ==> NC */ /* D13 : ISH_UART0_RXD ==> NC */
PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG),
/* D14 : ISH_UART0_TXD ==> NC */ /* D14 : ISH_UART0_TXD ==> NC */