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Documentation/Intel/NativeRaminit: Style fixes 

Fix tables and minor markdown bugs.

Change-Id: I2ceb9614b516cbea19ab5e15ea7efabdfa3424bd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/26276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Patrick Rudolph 2018-05-14 19:17:05 +02:00 committed by Martin Roth
parent 5dbe8ee725
commit ebdeb4d07d
4 changed files with 1474 additions and 645 deletions
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1058
Documentation/Intel/NativeRaminit/SandyBridge_registers.md
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25
Documentation/Intel/NativeRaminit/Sandybridge.md
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@ -18,16 +18,27 @@ The memory initialization code has to take care of lots of duties:
* Error handling
## Definitions
```eval_rst
+---------+-------------------------------------------------------------------+------------+--------------+
| Symbol | Description | Units | Valid region |
|---------|-------------------------------------------------------------------|------------|--------------|
| SCK | DRAM system clock cycle time | s | - |
| tCK | DRAM system clock cycle time | 1/256th ns | - |
| DCK | Data clock cycle time: The time between two SCK clock edges | s | - |
+=========+===================================================================+============+==============+
| SCK | DRAM system clock cycle time | s | |
+---------+-------------------------------------------------------------------+------------+--------------+
| tCK | DRAM system clock cycle time | 1/256th ns | |
+---------+-------------------------------------------------------------------+------------+--------------+
| DCK | Data clock cycle time: The time between two SCK clock edges | s | |
+---------+-------------------------------------------------------------------+------------+--------------+
| timA | IO phase: The phase delay of the IO signals | 1/64th DCK | [0-512) |
| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | - |
+---------+-------------------------------------------------------------------+------------+--------------+
| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | |
+---------+-------------------------------------------------------------------+------------+--------------+
| REFCK | Reference clock, either 100 or 133 | Mhz | 100, 133 |
| MULT | DRAM PLL multiplier | - | [3-12] |
| XMP | Extreme Memory Profiles | - | - |
+---------+-------------------------------------------------------------------+------------+--------------+
| MULT | DRAM PLL multiplier | | [3-12] |
+---------+-------------------------------------------------------------------+------------+--------------+
| XMP | Extreme Memory Profiles | | |
+---------+-------------------------------------------------------------------+------------+--------------+
```
## (Inoffical) register documentation
- [Sandy Bride - Register documentation](SandyBridge_registers.md)

63
Documentation/Intel/NativeRaminit/Sandybridge_freq.md
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@ -4,16 +4,25 @@
This chapter explains the frequency selection done on Sandybride and Ivybridge.
## Definitions
```eval_rst
+---------+-------------------------------------------------------------------+------------+--------------+
| Symbol | Description | Units | Valid region |
|---------|-------------------------------------------------------------------|------------|--------------|
| SCK | DRAM system clock cycle time | s | - |
| tCK | DRAM system clock cycle time | 1/256th ns | - |
| DCK | Data clock cycle time: The time between two SCK clock edges | s | - |
| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | - |
| REFCK | Reference clock, either 100 or 133 | Mhz | 100, 133 |
| MULT | DRAM PLL multiplier | - | [3-12] |
| XMP | Extreme Memory Profiles | - | - |
+=========+===================================================================+============+==============+
| SCK | DRAM system clock cycle time | s | |
+---------+-------------------------------------------------------------------+------------+--------------+
| tCK | DRAM system clock cycle time | 1/256th ns | |
+---------+-------------------------------------------------------------------+------------+--------------+
| DCK | Data clock cycle time: The time between two SCK clock edges | s | |
+---------+-------------------------------------------------------------------+------------+--------------+
| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | |
+---------+-------------------------------------------------------------------+------------+--------------+
| REFCK | Reference clock, either 100 or 133 | MHz | 100, 133 |
+---------+-------------------------------------------------------------------+------------+--------------+
| MULT | DRAM PLL multiplier | | [3-12] |
+---------+-------------------------------------------------------------------+------------+--------------+
| XMP | Extreme Memory Profiles | | |
+---------+-------------------------------------------------------------------+------------+--------------+
```
## SPD
The [SPD](https://de.wikipedia.org/wiki/Serial_Presence_Detect "Serial Presence Detect")
located on every DIMM is factory program with various timings. One of them
@ -84,31 +93,54 @@ multiplier to select the DRAM frequency (SCK) by the following formula:
> **Note:** Since coreboot 4.6 Ivy Bridge supports 100MHz REFCK.
## Sandy Bride's supported frequencies
```eval_rst
+------------+-----------+------------------+-------------------------+---------------+
| SCK [Mhz] | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment |
|------------|-----------|------------------|-------------------------|---------------|
+============+===========+==================+=========================+===============+
| 400 | DDR3-800 | 3 | 133 MHz | |
+------------+-----------+------------------+-------------------------+---------------+
| 533 | DDR3-1066 | 4 | 133 MHz | |
+------------+-----------+------------------+-------------------------+---------------+
| 666 | DDR3-1333 | 5 | 133 MHz | |
+------------+-----------+------------------+-------------------------+---------------+
| 800 | DDR3-1600 | 6 | 133 MHz | |
+------------+-----------+------------------+-------------------------+---------------+
| 933 | DDR3-1866 | 7 | 133 MHz | |
| 1066 | DDR3-2166 | 8 | 133 MHz | ||
+------------+-----------+------------------+-------------------------+---------------+
| 1066 | DDR3-2166 | 8 | 133 MHz | |
+------------+-----------+------------------+-------------------------+---------------+
```
## Ivybridge's supported frequencies
```eval_rst
+------------+-----------+------------------+-------------------------+---------------+
| SCK [Mhz] | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment |
|------------|-----------|------------------|-------------------------|---------------|
+============+===========+==================+=========================+===============+
| 400 | DDR3-800 | 3 | 133 MHz | |
+------------+-----------+------------------+-------------------------+---------------+
| 533 | DDR3-1066 | 4 | 133 MHz | |
+------------+-----------+------------------+-------------------------+---------------+
| 666 | DDR3-1333 | 5 | 133 MHz | |
+------------+-----------+------------------+-------------------------+---------------+
| 800 | DDR3-1600 | 6 | 133 MHz | |
+------------+-----------+------------------+-------------------------+---------------+
| 933 | DDR3-1866 | 7 | 133 MHz | |
+------------+-----------+------------------+-------------------------+---------------+
| 1066 | DDR3-2166 | 8 | 133 MHz | |
+------------+-----------+------------------+-------------------------+---------------+
| 700 | DDR3-1400 | 7 | 100 MHz | '1 |
+------------+-----------+------------------+-------------------------+---------------+
| 800 | DDR3-1600 | 8 | 100 MHz | '1 |
+------------+-----------+------------------+-------------------------+---------------+
| 900 | DDR3-1800 | 9 | 100 MHz | '1 |
+------------+-----------+------------------+-------------------------+---------------+
| 1000 | DDR3-2000 | 10 | 100 MHz | '1 |
+------------+-----------+------------------+-------------------------+---------------+
| 1100 | DDR3-2200 | 11 | 100 MHz | '1 |
| 1200 | DDR3-2400 | 12 | 100 MHz | '1 ||
+------------+-----------+------------------+-------------------------+---------------+
| 1200 | DDR3-2400 | 12 | 100 MHz | '1 |
+------------+-----------+------------------+-------------------------+---------------+
```
> '1: since coreboot 4.6
## Multiplier selection
@ -120,7 +152,8 @@ else:
freq_max := soft_fuse_max_mhz
for i in SPDs:
freq_max := MIN(freq_max, ddr_spd_max_mhz[i])```
freq_max := MIN(freq_max, ddr_spd_max_mhz[i])
```
As you can see, by using DIMMs with different maximum DRAM frequencies, the
slowest DIMMs' frequency will be selected, to prevent over-clocking it.

37
Documentation/Intel/NativeRaminit/Sandybridge_read.md
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@ -23,18 +23,29 @@ actual delay of every lane can be measured.
The values programmed in read training effect DRAM-to-MC transfers only !
## Definitions
```eval_rst
+---------+-------------------------------------------------------------------+------------+--------------+
| Symbol | Description | Units | Valid region |
|---------|-------------------------------------------------------------------|------------|--------------|
| SCK | DRAM system clock cycle time | s | - |
| tCK | DRAM system clock cycle time | 1/256th ns | - |
| DCK | Data clock cycle time: The time between two SCK clock edges | s | - |
+=========+===================================================================+============+==============+
| SCK | DRAM system clock cycle time | s | |
+---------+-------------------------------------------------------------------+------------+--------------+
| tCK | DRAM system clock cycle time | 1/256th ns | |
+---------+-------------------------------------------------------------------+------------+--------------+
| DCK | Data clock cycle time: The time between two SCK clock edges | s | |
+---------+-------------------------------------------------------------------+------------+--------------+
| timA | IO phase: The phase delay of the IO signals | 1/64th DCK | [0-512) |
| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | - |
| REFCK | Reference clock, either 100 or 133 | Mhz | 100, 133 |
| MULT | DRAM PLL multiplier | - | [3-12] |
| XMP | Extreme Memory Profiles | - | - |
| DQS | Data Strobe signal used to sample all lane's DQ signals | - | - |
+---------+-------------------------------------------------------------------+------------+--------------+
| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | |
+---------+-------------------------------------------------------------------+------------+--------------+
| REFCK | Reference clock, either 100 or 133 | MHz | 100, 133 |
+---------+-------------------------------------------------------------------+------------+--------------+
| MULT | DRAM PLL multiplier | | [3-12] |
+---------+-------------------------------------------------------------------+------------+--------------+
| XMP | Extreme Memory Profiles | | |
+---------+-------------------------------------------------------------------+------------+--------------+
| DQS | Data Strobe signal used to sample all lane's DQ signals | | |
+---------+-------------------------------------------------------------------+------------+--------------+
```
## Hardware
The hardware does have delay logic blocks that can delay the DQ / DQS of a
lane/rank by one or multiple clock cylces and it does have delay logic blocks
@ -66,18 +77,18 @@ The picture was generated from 16 IO delay values times 64 timA values.
The highest IO delay was set on the right-hand side, while the last block
on the left-hand side has zero IO delay.
** roundtrip 55 DCKs **
#### roundtrip 55 DCKs
![alt text][timA_lane0-3_rt55]
[timA_lane0-3_rt55]: timA_lane0-3_rt55.png "timA for lane0 - lane3, roundtrip 55"
** roundtrip 54 DCKs **
#### roundtrip 54 DCKs
![alt text][timA_lane0-3_rt54]
[timA_lane0-3_rt54]: timA_lane0-3_rt54.png "timA for lane0 - lane3, roundtrip 54"
** roundtrip 53 DCKs **
#### roundtrip 53 DCKs
![alt text][timA_lane0-3_rt53]
[timA_lane0-3_rt53]: timA_lane0-3_rt53.png "timA for lane0 - lane3, roundtrip 53"