Documentation/Intel/NativeRaminit: Style fixes
Fix tables and minor markdown bugs. Change-Id: I2ceb9614b516cbea19ab5e15ea7efabdfa3424bd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/26276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -18,16 +18,27 @@ The memory initialization code has to take care of lots of duties:
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* Error handling
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## Definitions
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```eval_rst
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+---------+-------------------------------------------------------------------+------------+--------------+
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| Symbol | Description | Units | Valid region |
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|---------|-------------------------------------------------------------------|------------|--------------|
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| SCK | DRAM system clock cycle time | s | - |
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| tCK | DRAM system clock cycle time | 1/256th ns | - |
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| DCK | Data clock cycle time: The time between two SCK clock edges | s | - |
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+=========+===================================================================+============+==============+
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| SCK | DRAM system clock cycle time | s | |
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+---------+-------------------------------------------------------------------+------------+--------------+
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| tCK | DRAM system clock cycle time | 1/256th ns | |
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+---------+-------------------------------------------------------------------+------------+--------------+
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| DCK | Data clock cycle time: The time between two SCK clock edges | s | |
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+---------+-------------------------------------------------------------------+------------+--------------+
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| timA | IO phase: The phase delay of the IO signals | 1/64th DCK | [0-512) |
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| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | - |
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+---------+-------------------------------------------------------------------+------------+--------------+
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| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | |
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+---------+-------------------------------------------------------------------+------------+--------------+
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| REFCK | Reference clock, either 100 or 133 | Mhz | 100, 133 |
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| MULT | DRAM PLL multiplier | - | [3-12] |
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| XMP | Extreme Memory Profiles | - | - |
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+---------+-------------------------------------------------------------------+------------+--------------+
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| MULT | DRAM PLL multiplier | | [3-12] |
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+---------+-------------------------------------------------------------------+------------+--------------+
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| XMP | Extreme Memory Profiles | | |
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+---------+-------------------------------------------------------------------+------------+--------------+
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```
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## (Inoffical) register documentation
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- [Sandy Bride - Register documentation](SandyBridge_registers.md)
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@ -4,16 +4,25 @@
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This chapter explains the frequency selection done on Sandybride and Ivybridge.
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## Definitions
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```eval_rst
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+---------+-------------------------------------------------------------------+------------+--------------+
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| Symbol | Description | Units | Valid region |
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|---------|-------------------------------------------------------------------|------------|--------------|
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| SCK | DRAM system clock cycle time | s | - |
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| tCK | DRAM system clock cycle time | 1/256th ns | - |
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| DCK | Data clock cycle time: The time between two SCK clock edges | s | - |
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| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | - |
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| REFCK | Reference clock, either 100 or 133 | Mhz | 100, 133 |
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| MULT | DRAM PLL multiplier | - | [3-12] |
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| XMP | Extreme Memory Profiles | - | - |
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+=========+===================================================================+============+==============+
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| SCK | DRAM system clock cycle time | s | |
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+---------+-------------------------------------------------------------------+------------+--------------+
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| tCK | DRAM system clock cycle time | 1/256th ns | |
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+---------+-------------------------------------------------------------------+------------+--------------+
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| DCK | Data clock cycle time: The time between two SCK clock edges | s | |
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+---------+-------------------------------------------------------------------+------------+--------------+
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| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | |
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+---------+-------------------------------------------------------------------+------------+--------------+
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| REFCK | Reference clock, either 100 or 133 | MHz | 100, 133 |
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+---------+-------------------------------------------------------------------+------------+--------------+
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| MULT | DRAM PLL multiplier | | [3-12] |
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+---------+-------------------------------------------------------------------+------------+--------------+
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| XMP | Extreme Memory Profiles | | |
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+---------+-------------------------------------------------------------------+------------+--------------+
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```
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## SPD
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The [SPD](https://de.wikipedia.org/wiki/Serial_Presence_Detect "Serial Presence Detect")
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located on every DIMM is factory program with various timings. One of them
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@ -84,31 +93,54 @@ multiplier to select the DRAM frequency (SCK) by the following formula:
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> **Note:** Since coreboot 4.6 Ivy Bridge supports 100MHz REFCK.
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## Sandy Bride's supported frequencies
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```eval_rst
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+------------+-----------+------------------+-------------------------+---------------+
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| SCK [Mhz] | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment |
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|------------|-----------|------------------|-------------------------|---------------|
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+============+===========+==================+=========================+===============+
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| 400 | DDR3-800 | 3 | 133 MHz | |
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+------------+-----------+------------------+-------------------------+---------------+
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| 533 | DDR3-1066 | 4 | 133 MHz | |
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+------------+-----------+------------------+-------------------------+---------------+
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| 666 | DDR3-1333 | 5 | 133 MHz | |
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+------------+-----------+------------------+-------------------------+---------------+
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| 800 | DDR3-1600 | 6 | 133 MHz | |
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+------------+-----------+------------------+-------------------------+---------------+
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| 933 | DDR3-1866 | 7 | 133 MHz | |
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| 1066 | DDR3-2166 | 8 | 133 MHz | ||
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+------------+-----------+------------------+-------------------------+---------------+
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| 1066 | DDR3-2166 | 8 | 133 MHz | |
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+------------+-----------+------------------+-------------------------+---------------+
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```
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## Ivybridge's supported frequencies
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```eval_rst
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+------------+-----------+------------------+-------------------------+---------------+
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| SCK [Mhz] | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment |
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|------------|-----------|------------------|-------------------------|---------------|
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+============+===========+==================+=========================+===============+
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| 400 | DDR3-800 | 3 | 133 MHz | |
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+------------+-----------+------------------+-------------------------+---------------+
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| 533 | DDR3-1066 | 4 | 133 MHz | |
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+------------+-----------+------------------+-------------------------+---------------+
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| 666 | DDR3-1333 | 5 | 133 MHz | |
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+------------+-----------+------------------+-------------------------+---------------+
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| 800 | DDR3-1600 | 6 | 133 MHz | |
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+------------+-----------+------------------+-------------------------+---------------+
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| 933 | DDR3-1866 | 7 | 133 MHz | |
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+------------+-----------+------------------+-------------------------+---------------+
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| 1066 | DDR3-2166 | 8 | 133 MHz | |
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+------------+-----------+------------------+-------------------------+---------------+
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| 700 | DDR3-1400 | 7 | 100 MHz | '1 |
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+------------+-----------+------------------+-------------------------+---------------+
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| 800 | DDR3-1600 | 8 | 100 MHz | '1 |
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+------------+-----------+------------------+-------------------------+---------------+
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| 900 | DDR3-1800 | 9 | 100 MHz | '1 |
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+------------+-----------+------------------+-------------------------+---------------+
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| 1000 | DDR3-2000 | 10 | 100 MHz | '1 |
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+------------+-----------+------------------+-------------------------+---------------+
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| 1100 | DDR3-2200 | 11 | 100 MHz | '1 |
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| 1200 | DDR3-2400 | 12 | 100 MHz | '1 ||
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+------------+-----------+------------------+-------------------------+---------------+
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| 1200 | DDR3-2400 | 12 | 100 MHz | '1 |
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+------------+-----------+------------------+-------------------------+---------------+
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```
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> '1: since coreboot 4.6
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## Multiplier selection
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@ -120,7 +152,8 @@ else:
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freq_max := soft_fuse_max_mhz
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for i in SPDs:
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freq_max := MIN(freq_max, ddr_spd_max_mhz[i])```
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freq_max := MIN(freq_max, ddr_spd_max_mhz[i])
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```
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As you can see, by using DIMMs with different maximum DRAM frequencies, the
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slowest DIMMs' frequency will be selected, to prevent over-clocking it.
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@ -23,18 +23,29 @@ actual delay of every lane can be measured.
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The values programmed in read training effect DRAM-to-MC transfers only !
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## Definitions
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```eval_rst
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+---------+-------------------------------------------------------------------+------------+--------------+
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| Symbol | Description | Units | Valid region |
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|---------|-------------------------------------------------------------------|------------|--------------|
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| SCK | DRAM system clock cycle time | s | - |
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| tCK | DRAM system clock cycle time | 1/256th ns | - |
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| DCK | Data clock cycle time: The time between two SCK clock edges | s | - |
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+=========+===================================================================+============+==============+
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| SCK | DRAM system clock cycle time | s | |
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+---------+-------------------------------------------------------------------+------------+--------------+
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| tCK | DRAM system clock cycle time | 1/256th ns | |
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+---------+-------------------------------------------------------------------+------------+--------------+
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| DCK | Data clock cycle time: The time between two SCK clock edges | s | |
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+---------+-------------------------------------------------------------------+------------+--------------+
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| timA | IO phase: The phase delay of the IO signals | 1/64th DCK | [0-512) |
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| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | - |
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| REFCK | Reference clock, either 100 or 133 | Mhz | 100, 133 |
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| MULT | DRAM PLL multiplier | - | [3-12] |
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| XMP | Extreme Memory Profiles | - | - |
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| DQS | Data Strobe signal used to sample all lane's DQ signals | - | - |
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+---------+-------------------------------------------------------------------+------------+--------------+
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| SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | |
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+---------+-------------------------------------------------------------------+------------+--------------+
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| REFCK | Reference clock, either 100 or 133 | MHz | 100, 133 |
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+---------+-------------------------------------------------------------------+------------+--------------+
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| MULT | DRAM PLL multiplier | | [3-12] |
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+---------+-------------------------------------------------------------------+------------+--------------+
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| XMP | Extreme Memory Profiles | | |
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+---------+-------------------------------------------------------------------+------------+--------------+
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| DQS | Data Strobe signal used to sample all lane's DQ signals | | |
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+---------+-------------------------------------------------------------------+------------+--------------+
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```
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## Hardware
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The hardware does have delay logic blocks that can delay the DQ / DQS of a
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lane/rank by one or multiple clock cylces and it does have delay logic blocks
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The highest IO delay was set on the right-hand side, while the last block
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on the left-hand side has zero IO delay.
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** roundtrip 55 DCKs **
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#### roundtrip 55 DCKs
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![alt text][timA_lane0-3_rt55]
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[timA_lane0-3_rt55]: timA_lane0-3_rt55.png "timA for lane0 - lane3, roundtrip 55"
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** roundtrip 54 DCKs **
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#### roundtrip 54 DCKs
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![alt text][timA_lane0-3_rt54]
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[timA_lane0-3_rt54]: timA_lane0-3_rt54.png "timA for lane0 - lane3, roundtrip 54"
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** roundtrip 53 DCKs **
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#### roundtrip 53 DCKs
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![alt text][timA_lane0-3_rt53]
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[timA_lane0-3_rt53]: timA_lane0-3_rt53.png "timA for lane0 - lane3, roundtrip 53"
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