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drivers/intel/gma/opregion: migrate from nb/common 

Migrate opregion code from northbridge/intel/common to
drivers/intel/gma in preparation for consolidation with
soc/intel/common opregion code. Rename init_igd_opregion()
for clarity and disambiguation with other implementations.

Change-Id: I2d0bae98f04dbe7e896ca34e15f24d29b6aa2ed6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Matt DeVillier 2017-07-14 13:28:42 -05:00 committed by Martin Roth
parent 44d399c394
commit ebe08e0ee3
15 changed files with 114 additions and 167 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/drivers/intel/gma/Makefile.inc
View File

@ -21,7 +21,6 @@ endif
ramstage-$(CONFIG_INTEL_GMA_ACPI) += acpi.c
ramstage-$(CONFIG_INTEL_GMA_ACPI) += opregion.c
ifeq ($(CONFIG_MAINBOARD_USE_LIBGFXINIT),y)
$(call add-special-class,gfxinit)

105
src/drivers/intel/gma/opregion.c
View File

@ -14,12 +14,16 @@
* GNU General Public License for more details.
*/
#include <arch/acpi.h>
#include <types.h>
#include <string.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <cbmem.h>
#include "intel_bios.h"
#include "opregion.h"
/* Write ASLS PCI register and prepare SWSCI register. */
@ -62,3 +66,104 @@ void intel_gma_restore_opregion(void)
printk(BIOS_ERR, "Error: GNVS or ASLB not set.\n");
}
}
static void *get_intel_vbios(void)
{
/* This should probably be looking at CBFS or we should always
* deploy the VBIOS on Intel systems, even if we don't run it
* in coreboot (e.g. SeaBIOS only scenarios).
*/
u8 *vbios = (u8 *)0xc0000;
optionrom_header_t *oprom = (optionrom_header_t *)vbios;
optionrom_pcir_t *pcir = (optionrom_pcir_t *)(vbios +
oprom->pcir_offset);
printk(BIOS_DEBUG, "GET_VBIOS: %x %x %x %x %x\n",
oprom->signature, pcir->vendor, pcir->classcode[0],
pcir->classcode[1], pcir->classcode[2]);
if ((oprom->signature == OPROM_SIGNATURE) &&
(pcir->vendor == PCI_VENDOR_ID_INTEL) &&
(pcir->classcode[0] == 0x00) &&
(pcir->classcode[1] == 0x00) &&
(pcir->classcode[2] == 0x03))
return (void *)vbios;
return NULL;
}
static enum cb_err init_opregion_vbt(igd_opregion_t *opregion)
{
void *vbios;
vbios = get_intel_vbios();
if (!vbios) {
printk(BIOS_DEBUG, "VBIOS not found.\n");
return CB_ERR;
}
printk(BIOS_DEBUG, " ... VBIOS found at %p\n", vbios);
optionrom_header_t *oprom = (optionrom_header_t *)vbios;
optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios +
oprom->vbt_offset);
if (read32(vbt->hdr_signature) != VBT_SIGNATURE) {
printk(BIOS_DEBUG, "VBT not found!\n");
return CB_ERR;
}
memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4);
memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < 7168 ?
vbt->hdr_vbt_size : 7168);
return CB_SUCCESS;
}
/* Initialize IGD OpRegion, called from ACPI code and OS drivers */
enum cb_err intel_gma_init_igd_opregion(igd_opregion_t *opregion)
{
enum cb_err ret;
memset((void *)opregion, 0, sizeof(igd_opregion_t));
// FIXME if IGD is disabled, we should exit here.
memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
sizeof(opregion->header.signature));
/* 8kb */
opregion->header.size = sizeof(igd_opregion_t) / 1024;
opregion->header.version = IGD_OPREGION_VERSION;
// FIXME We just assume we're mobile for now
opregion->header.mailboxes = MAILBOXES_MOBILE;
// TODO Initialize Mailbox 1
// TODO Initialize Mailbox 3
opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
opregion->mailbox3.pcft = 0; // should be (IMON << 1) & 0x3e
opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
ret = init_opregion_vbt(opregion);
if (ret != CB_SUCCESS)
return ret;
/* Write ASLS PCI register and prepare SWSCI register. */
intel_gma_opregion_register((uintptr_t)opregion);
return CB_SUCCESS;
}

1
src/drivers/intel/gma/opregion.h
View File

@ -250,5 +250,6 @@ void intel_gma_opregion_register(uintptr_t opregion);
void intel_gma_restore_opregion(void);
uintptr_t gma_get_gnvs_aslb(const void *gnvs);
void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb);
enum cb_err intel_gma_init_igd_opregion(igd_opregion_t *opregion);
#endif /* _COMMON_GMA_H_ */

3
src/northbridge/intel/common/Kconfig
View File

@ -1,5 +1,2 @@
config NORTHBRIDGE_INTEL_COMMON_MRC_CACHE
def_bool n
config NORTHBRIDGE_INTEL_COMMON_GMA_OPREGION
def_bool n

1
src/northbridge/intel/common/Makefile.inc
View File

@ -15,4 +15,3 @@
romstage-$(CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE) += mrc_cache.c
ramstage-$(CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE) += mrc_cache.c
ramstage-$(CONFIG_NORTHBRIDGE_INTEL_COMMON_GMA_OPREGION) += gma_opregion.c

124
src/northbridge/intel/common/gma_opregion.c
View File

@ -1,124 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Patrick Rudolph <siro@das-labor.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <types.h>
#include <string.h>
#include <console/console.h>
#include <arch/acpi.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <drivers/intel/gma/intel_bios.h>
#include "gma_opregion.h"
static void *get_intel_vbios(void)
{
/* This should probably be looking at CBFS or we should always
* deploy the VBIOS on Intel systems, even if we don't run it
* in coreboot (e.g. SeaBIOS only scenarios).
*/
u8 *vbios = (u8 *)0xc0000;
optionrom_header_t *oprom = (optionrom_header_t *)vbios;
optionrom_pcir_t *pcir = (optionrom_pcir_t *)(vbios +
oprom->pcir_offset);
printk(BIOS_DEBUG, "GET_VBIOS: %x %x %x %x %x\n",
oprom->signature, pcir->vendor, pcir->classcode[0],
pcir->classcode[1], pcir->classcode[2]);
if ((oprom->signature == OPROM_SIGNATURE) &&
(pcir->vendor == PCI_VENDOR_ID_INTEL) &&
(pcir->classcode[0] == 0x00) &&
(pcir->classcode[1] == 0x00) &&
(pcir->classcode[2] == 0x03))
return (void *)vbios;
return NULL;
}
static enum cb_err init_opregion_vbt(igd_opregion_t *opregion)
{
void *vbios;
vbios = get_intel_vbios();
if (!vbios) {
printk(BIOS_DEBUG, "VBIOS not found.\n");
return CB_ERR;
}
printk(BIOS_DEBUG, " ... VBIOS found at %p\n", vbios);
optionrom_header_t *oprom = (optionrom_header_t *)vbios;
optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios +
oprom->vbt_offset);
if (read32(vbt->hdr_signature) != VBT_SIGNATURE) {
printk(BIOS_DEBUG, "VBT not found!\n");
return CB_ERR;
}
memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4);
memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < 7168 ?
vbt->hdr_vbt_size : 7168);
return CB_SUCCESS;
}
/* Initialize IGD OpRegion, called from ACPI code and OS drivers */
enum cb_err init_igd_opregion(igd_opregion_t *opregion)
{
enum cb_err ret;
memset((void *)opregion, 0, sizeof(igd_opregion_t));
// FIXME if IGD is disabled, we should exit here.
memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
sizeof(opregion->header.signature));
/* 8kb */
opregion->header.size = sizeof(igd_opregion_t) / 1024;
opregion->header.version = IGD_OPREGION_VERSION;
// FIXME We just assume we're mobile for now
opregion->header.mailboxes = MAILBOXES_MOBILE;
// TODO Initialize Mailbox 1
// TODO Initialize Mailbox 3
opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
opregion->mailbox3.pcft = 0; // should be (IMON << 1) & 0x3e
opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
ret = init_opregion_vbt(opregion);
if (ret != CB_SUCCESS)
return ret;
/* Write ASLS PCI register and prepare SWSCI register. */
intel_gma_opregion_register((uintptr_t)opregion);
return CB_SUCCESS;
}

24
src/northbridge/intel/common/gma_opregion.h
View File

@ -1,24 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Patrick Rudolph <siro@das-labor.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef NORTHBRIDGE_INTEL_COMMON_GMA_OPREGION_H_
#define NORTHBRIDGE_INTEL_COMMON_GMA_OPREGION_H_
#include <types.h>
#include <drivers/intel/gma/opregion.h>
enum cb_err init_igd_opregion(igd_opregion_t *opregion);
#endif /* NORTHBRIDGE_INTEL_COMMON_GMA_OPREGION_H_ */

2
src/northbridge/intel/fsp_sandybridge/Kconfig
View File

@ -18,13 +18,11 @@ config NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE
bool
select CPU_INTEL_FSP_MODEL_206AX
select INTEL_GMA_ACPI
select NORTHBRIDGE_INTEL_COMMON_GMA_OPREGION
config NORTHBRIDGE_INTEL_FSP_IVYBRIDGE
bool
select CPU_INTEL_FSP_MODEL_306AX
select INTEL_GMA_ACPI
select NORTHBRIDGE_INTEL_COMMON_GMA_OPREGION
if NORTHBRIDGE_INTEL_FSP_IVYBRIDGE || NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE

4
src/northbridge/intel/fsp_sandybridge/gma.c
View File

@ -20,7 +20,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <southbridge/intel/fsp_bd82x6x/nvs.h>
#include <northbridge/intel/common/gma_opregion.h>
#include <drivers/intel/gma/opregion.h>
#include <drivers/intel/gma/intel_bios.h>
#include <cbmem.h>
@ -133,7 +133,7 @@ gma_write_acpi_tables(struct device *const dev,
igd_opregion_t *opregion = (igd_opregion_t *)current;
global_nvs_t *gnvs;
if (init_igd_opregion(opregion) != CB_SUCCESS)
if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
return current;
current += sizeof(igd_opregion_t);

1
src/northbridge/intel/haswell/Kconfig
View File

@ -17,7 +17,6 @@ config NORTHBRIDGE_INTEL_HASWELL
bool
select CPU_INTEL_HASWELL
select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE
select NORTHBRIDGE_INTEL_COMMON_GMA_OPREGION
select INTEL_DDI
select INTEL_GMA_ACPI
select RELOCATABLE_RAMSTAGE

4
src/northbridge/intel/haswell/gma.c
View File

@ -24,7 +24,7 @@
#include <drivers/intel/gma/i915_reg.h>
#include <drivers/intel/gma/i915.h>
#include <cpu/intel/haswell/haswell.h>
#include <northbridge/intel/common/gma_opregion.h>
#include <drivers/intel/gma/opregion.h>
#include <southbridge/intel/lynxpoint/nvs.h>
#include <stdlib.h>
#include <string.h>
@ -534,7 +534,7 @@ gma_write_acpi_tables(struct device *const dev,
igd_opregion_t *opregion = (igd_opregion_t *)current;
global_nvs_t *gnvs;
if (init_igd_opregion(opregion) != CB_SUCCESS)
if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
return current;
current += sizeof(igd_opregion_t);

1
src/northbridge/intel/nehalem/Kconfig
View File

@ -21,7 +21,6 @@ config NORTHBRIDGE_INTEL_NEHALEM
select TSC_MONOTONIC_TIMER
select INTEL_GMA_ACPI
select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE
select NORTHBRIDGE_INTEL_COMMON_GMA_OPREGION
select ACPI_HUGE_LOWMEM_BACKUP
select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT

4
src/northbridge/intel/nehalem/gma.c
View File

@ -30,7 +30,7 @@
#include <pc80/vga.h>
#include <pc80/vga_io.h>
#include <southbridge/intel/ibexpeak/nvs.h>
#include <northbridge/intel/common/gma_opregion.h>
#include <drivers/intel/gma/opregion.h>
#include <cbmem.h>
#include "chip.h"
@ -1143,7 +1143,7 @@ gma_write_acpi_tables(struct device *const dev,
igd_opregion_t *opregion = (igd_opregion_t *)current;
global_nvs_t *gnvs;
if (init_igd_opregion(opregion) != CB_SUCCESS)
if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
return current;
current += sizeof(igd_opregion_t);

2
src/northbridge/intel/sandybridge/Kconfig
View File

@ -17,7 +17,6 @@
config NORTHBRIDGE_INTEL_SANDYBRIDGE
bool
select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE
select NORTHBRIDGE_INTEL_COMMON_GMA_OPREGION
select CPU_INTEL_MODEL_206AX
select HAVE_DEBUG_RAM_SETUP
select INTEL_GMA_ACPI
@ -26,7 +25,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE
config NORTHBRIDGE_INTEL_IVYBRIDGE
bool
select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE
select NORTHBRIDGE_INTEL_COMMON_GMA_OPREGION
select CPU_INTEL_MODEL_306AX
select HAVE_DEBUG_RAM_SETUP
select INTEL_GMA_ACPI

4
src/northbridge/intel/sandybridge/gma.c
View File

@ -25,7 +25,7 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include <northbridge/intel/common/gma_opregion.h>
#include <drivers/intel/gma/opregion.h>
#include <cbmem.h>
#include "chip.h"
@ -698,7 +698,7 @@ gma_write_acpi_tables(struct device *const dev,
igd_opregion_t *opregion = (igd_opregion_t *)current;
global_nvs_t *gnvs;
if (init_igd_opregion(opregion) != CB_SUCCESS)
if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
return current;
current += sizeof(igd_opregion_t);