baytrail: Add GPIO initial configuration infrastructure.
During ramstage, call mainboard_get_gpios to get initial GPIO configuration from the mainboard code, then initialize GPIOs as requested. BUG=chrome-os-partner:22863 TEST=Manual. Using bayleybay GPIO table, set UART GPIOs to 'function 1', and verify UART still works after GPIO configuration. Also, verify legacy GPIO config is functional by toggling test pin. Change-Id: Ic58d8ddd15c4dc48a751a83f6d26c7809c1efc42 Reviewed-on: https://chromium-review.googlesource.com/170306 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4855 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Shawn Nematbakhsh
Aaron Durbin
parent
c8f54a1109
commit
ebe3b3cfe2
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@ -18,7 +18,7 @@ ramstage-y += iosf.c
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romstage-y += iosf.c
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ramstage-y += northcluster.c
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ramstage-y += ramstage.c
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ramstage-y += gpio.c
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# Remove as ramstage gets fleshed out
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ramstage-y += placeholders.c
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@ -24,20 +24,181 @@
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#include <arch/io.h>
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#include <baytrail/iomap.h>
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/* Registers sitting behind the IO_BASE_ADDRESS */
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/* #define GPIO_DEBUG */
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#define SCORE_PCONF_OFFSET 0x0000
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#define SSUS_PCONF_OFFSET 0x2000
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/* Pad base, ex. PAD_CONF0[n]= PAD_BASE+16*n */
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#define GPSCORE_PAD_BASE IO_BASE_ADDRESS + 0x0000
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#define GPNCORE_PAD_BASE IO_BASE_ADDRESS + 0x1000
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#define GPSSUS_PAD_BASE IO_BASE_ADDRESS + 0x2000
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/* Pad register offset */
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#define PAD_CONF0_REG 0x0
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#define PAD_CONF1_REG 0x4
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#define PAD_VAL_REG 0x8
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/* Legacy IO register base */
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#define GPSCORE_LEGACY_BASE GPIO_BASE_ADDRESS + 0x00
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#define GPSSUS_LEGACY_BASE GPIO_BASE_ADDRESS + 0x80
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/* Some banks have no legacy GPIO interface */
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#define GP_LEGACY_BASE_NONE 0xFFFF
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#define LEGACY_USE_SEL_REG 0x00
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#define LEGACY_IO_SEL_REG 0x04
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#define LEGACY_GP_LVL_REG 0x08
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#define LEGACY_TPE_REG 0x0C
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#define LEGACY_TNE_REG 0x10
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#define LEGACY_TS_REG 0x14
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#define LEGACY_WAKE_EN_REG 0x18
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/* Number of GPIOs in each bank */
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#define GPNCORE_COUNT 27
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#define GPSCORE_COUNT 102
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#define GPSSUS_COUNT 44
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/* GPIO legacy IO register settings */
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#define GPIO_USE_PAD 0
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#define GPIO_USE_LEGACY 1
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#define GPIO_DIR_OUTPUT 0
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#define GPIO_DIR_INPUT 1
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#define GPIO_LEVEL_LOW 0
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#define GPIO_LEVEL_HIGH 1
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#define GPIO_PEDGE_DISABLE 0
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#define GPIO_PEDGE_ENABLE 1
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#define GPIO_NEDGE_DISABLE 0
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#define GPIO_NEDGE_ENABLE 1
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/* PAD_CONF0 settings */
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#define PAD_IRQ_EN (1 << 27)
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#define PAD_LEVEL_IRQ (1 << 24)
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#define PAD_PU_2K (0 << 9)
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#define PAD_PU_10K (1 << 9)
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#define PAD_PU_20K (2 << 9)
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#define PAD_PU_40K (3 << 9)
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#define PAD_PU_DISABLE (0 << 7)
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#define PAD_PU_UP (1 << 7)
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#define PAD_PU_DOWN (2 << 7)
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#define PAD_FUNC0 0x0
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#define PAD_FUNC1 0x1
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#define PAD_FUNC2 0x2
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#define PAD_FUNC3 0x3
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#define PAD_FUNC4 0x4
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#define PAD_FUNC5 0x5
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#define PAD_FUNC6 0x6
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/* PAD_VAL settings */
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#define PAD_INPUT_ENABLE (1 << 2)
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#define PAD_OUTPUT_ENABLE (1 << 1)
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/* End marker */
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#define GPIO_LIST_END 0xffffffff
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#define GPIO_INPUT_PU_10K \
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{ .pad_conf0 = PAD_PU_10K | PAD_PU_UP, \
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.pad_val = PAD_INPUT_ENABLE, \
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.use_sel = GPIO_USE_LEGACY, \
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.io_sel = GPIO_DIR_INPUT }
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#define GPIO_OUT_LOW \
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{ .pad_conf0 = PAD_PU_DISABLE, \
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.pad_val = PAD_OUTPUT_ENABLE, \
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.use_sel = GPIO_USE_LEGACY, \
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.io_sel = GPIO_DIR_OUTPUT, \
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.gp_lvl = GPIO_LEVEL_LOW }
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#define GPIO_OUT_HIGH \
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{ .pad_conf0 = PAD_PU_DISABLE, \
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.pad_val = PAD_OUTPUT_ENABLE, \
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.use_sel = GPIO_USE_LEGACY, \
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.io_sel = GPIO_DIR_OUTPUT, \
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.gp_lvl = GPIO_LEVEL_HIGH }
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#define GPIO_FUNC0 \
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{ .use_sel = GPIO_USE_PAD, \
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.pad_conf0 = PAD_FUNC0 }
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#define GPIO_FUNC1 \
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{ .use_sel = GPIO_USE_PAD, \
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.pad_conf0 = PAD_FUNC1 }
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#define GPIO_FUNC2 \
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{ .use_sel = GPIO_USE_PAD, \
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.pad_conf0 = PAD_FUNC2 }
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#define GPIO_FUNC3 \
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{ .use_sel = GPIO_USE_PAD, \
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.pad_conf0 = PAD_FUNC3 }
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#define GPIO_FUNC4 \
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{ .use_sel = GPIO_USE_PAD, \
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.pad_conf0 = PAD_FUNC4 }
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#define GPIO_FUNC5 \
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{ .use_sel = GPIO_USE_PAD, \
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.pad_conf0 = PAD_FUNC5 }
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#define GPIO_FUNC6 \
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{ .use_sel = GPIO_USE_PAD, \
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.pad_conf0 = PAD_FUNC6 }
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#define GPIO_END \
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{ .pad_conf0 = GPIO_LIST_END }
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/* Common default GPIO settings */
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#define GPIO_INPUT GPIO_INPUT_PU_10K
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#define GPIO_UNUSED GPIO_INPUT_PU_10K
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#define GPIO_DEFAULT GPIO_FUNC0
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struct soc_gpio_map {
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u32 pad_conf0;
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u32 pad_conf1;
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u32 pad_val;
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u8 use_sel : 1;
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u8 io_sel : 1;
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u8 gp_lvl : 1;
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u8 tpe : 1;
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u8 tne : 1;
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u8 wake_en : 1;
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} __attribute__ ((packed));
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struct soc_gpio_config {
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const struct soc_gpio_map *ncore;
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const struct soc_gpio_map *score;
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const struct soc_gpio_map *ssus;
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};
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/* Description of GPIO 'bank' ex. {ncore, score. ssus} */
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struct gpio_bank {
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const int gpio_count;
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const u8* gpio_to_pad;
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const int legacy_base;
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const unsigned long pad_base;
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const u8 has_wake_en :1;
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};
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void setup_soc_gpios(struct soc_gpio_config *config);
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/* This function is weak and can be overridden by a mainboard function. */
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struct soc_gpio_config* mainboard_get_gpios(void);
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/* Functions / defines for changing GPIOs in romstage */
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/* SCORE Pad definitions. */
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#define PCU_SMB_CLK_PAD 88
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#define PCU_SMB_DATA_PAD 90
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static inline unsigned int score_pconf0(int pad_num)
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{
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return IO_BASE_ADDRESS + SCORE_PCONF_OFFSET + pad_num * 16;
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return GPSCORE_PAD_BASE + pad_num * 16;
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}
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static inline unsigned int ssus_pconf0(int pad_num)
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{
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return IO_BASE_ADDRESS + SSUS_PCONF_OFFSET + pad_num * 16;
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return GPSSUS_PAD_BASE + pad_num * 16;
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}
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static inline void score_select_func(int pad, int func)
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@ -62,9 +223,4 @@ static inline void ssus_select_func(int pad, int func)
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write32(pconf0_addr, reg);
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}
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/* SCORE Pad definitions. */
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#define PCU_SMB_CLK_PAD 88
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#define PCU_SMB_DATA_PAD 90
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#define PCU_SMB_ALERT_PAD 92
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#endif /* _BAYTRAIL_GPIO_H_ */
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@ -0,0 +1,166 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <baytrail/gpio.h>
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#include <device/pci.h>
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#include <console/console.h>
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/* GPIO-to-Pad LUTs */
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static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] =
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{ 25, 24, 23, 32, 33, 34, 36, 37, 35, 22,
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20, 21, 18, 38, 39, 1, 4, 8, 17, 0,
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3, 6, 16, 19, 2, 5, 9 };
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static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] =
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{ 85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
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36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
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54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
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52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
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95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
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86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
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80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
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2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
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31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
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24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
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97, 100 };
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static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] =
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{ 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
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18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
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0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
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26, 51, 56, 54, 49, 55, 48, 47, 50, 58,
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52, 53, 59, 40 };
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/* GPIO bank descriptions */
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static const struct gpio_bank gpncore_bank = {
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.gpio_count = GPNCORE_COUNT,
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.gpio_to_pad = gpncore_gpio_to_pad,
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.legacy_base = GP_LEGACY_BASE_NONE,
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.pad_base = GPNCORE_PAD_BASE,
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.has_wake_en = 0,
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};
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static const struct gpio_bank gpscore_bank = {
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.gpio_count = GPSCORE_COUNT,
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.gpio_to_pad = gpscore_gpio_to_pad,
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.legacy_base = GPSCORE_LEGACY_BASE,
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.pad_base = GPSCORE_PAD_BASE,
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.has_wake_en = 0,
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};
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static const struct gpio_bank gpssus_bank = {
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.gpio_count = GPSSUS_COUNT,
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.gpio_to_pad = gpssus_gpio_to_pad,
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.legacy_base = GPSSUS_LEGACY_BASE,
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.pad_base = GPSSUS_PAD_BASE,
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.has_wake_en = 1,
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};
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static void setup_gpios(const struct soc_gpio_map *gpios,
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const struct gpio_bank *bank)
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{
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const struct soc_gpio_map *config;
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int gpio = 0;
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u32 reg;
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u8 set, bit;
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u32 use_sel[4] = {0};
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u32 io_sel[4] = {0};
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u32 gp_lvl[4] = {0};
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u32 tpe[4] = {0};
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u32 tne[4] = {0};
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u32 wake_en[4] = {0};
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if (!gpios)
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return;
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for (config = gpios; config->pad_conf0 != GPIO_LIST_END;
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config++, gpio++) {
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if (gpio > bank->gpio_count)
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break;
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set = gpio >> 5;
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bit = gpio % 32;
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if (bank->legacy_base != GP_LEGACY_BASE_NONE) {
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/* Legacy IO configuration */
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use_sel[set] |= config->use_sel << bit;
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io_sel[set] |= config->io_sel << bit;
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gp_lvl[set] |= config->gp_lvl << bit;
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tpe[set] |= config->tpe << bit;
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tne[set] |= config->tne << bit;
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/* Some banks do not have wake_en ability */
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if (bank->has_wake_en)
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wake_en[set] |= config->wake_en << bit;
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}
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/* Pad configuration registers */
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reg = bank->pad_base + 16 * bank->gpio_to_pad[gpio];
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#ifdef GPIO_DEBUG
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printk(BIOS_DEBUG, "Write Pad: Base(%x) - %x %x %x\n",
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reg, config->pad_conf0, config->pad_conf1,
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config->pad_val );
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#endif
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write32(reg + PAD_CONF0_REG, config->pad_conf0);
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write32(reg + PAD_CONF1_REG, config->pad_conf1);
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write32(reg + PAD_VAL_REG, config->pad_val);
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}
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if (bank->legacy_base != GP_LEGACY_BASE_NONE)
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for (set = 0; set <= (bank->gpio_count - 1) / 32; ++set) {
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reg = bank->legacy_base + 0x20 * set;
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#ifdef GPIO_DEBUG
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printk(BIOS_DEBUG,
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"Write GPIO: Reg(%x) - %x %x %x %x %x\n",
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reg, use_sel[set], io_sel[set], gp_lvl[set],
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tpe[set], tne[set]);
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#endif
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outl(use_sel[set], reg + LEGACY_USE_SEL_REG);
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outl(io_sel[set], reg + LEGACY_IO_SEL_REG);
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outl(gp_lvl[set], reg + LEGACY_GP_LVL_REG);
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outl(tpe[set], reg + LEGACY_TPE_REG);
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outl(tne[set], reg + LEGACY_TNE_REG);
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/* TS registers are WOC */
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outl(0, reg + LEGACY_TS_REG);
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if (bank->has_wake_en)
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outl(wake_en[set], reg + LEGACY_WAKE_EN_REG);
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}
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}
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void setup_soc_gpios(struct soc_gpio_config *config)
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{
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if (config) {
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setup_gpios(config->ncore, &gpncore_bank);
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setup_gpios(config->score, &gpscore_bank);
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setup_gpios(config->ssus, &gpssus_bank);
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}
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}
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struct soc_gpio_config* __attribute__((weak)) mainboard_get_gpios(void)
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{
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printk(BIOS_DEBUG, "Default/empty GPIO config\n");
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return NULL;
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}
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@ -31,6 +31,7 @@
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#include <baytrail/msr.h>
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#include <baytrail/pci_devs.h>
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#include <baytrail/ramstage.h>
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#include <baytrail/gpio.h>
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/* Global PATTRS */
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DEFINE_PATTRS;
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@ -101,7 +102,14 @@ static void fill_in_pattrs(void)
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fill_in_msr(&attrs->iacore_vids, MSR_IACORE_VIDS);
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}
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void baytrail_init_pre_device(void)
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{
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struct soc_gpio_config *config;
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fill_in_pattrs();
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/* Get GPIO initial states from mainboard */
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config = mainboard_get_gpios();
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setup_soc_gpios(config);
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}
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