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sb/intel/bd82x6x: Use common final SPI OPs setup 

This also reworks the interface to override OPs from the devicetree to
match the interface in sb/intel/common/spi.

Change-Id: I534e989279d771ec4c0249af325bc3b30a661145
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Arthur Heymans 2019-05-28 13:51:36 +02:00 committed by Patrick Georgi
parent ff5eb86aeb
commit ebf201b8f5
4 changed files with 29 additions and 77 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/mainboard/sapphire/pureplatinumh61/devicetree.cb
View File

@ -55,7 +55,14 @@ chip northbridge/intel/sandybridge
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x33"
register "spi.opprefixes" = "{ 0x50, 0x06 }"
register "spi.ops" = "{ { 0, 1, 0x01 }, { 1, 1, 0x02 }, { 1, 0, 0x03 }, { 0, 0, 0x05 }, { 1, 1, 0x20 }, { 0, 0, 0x9f }, { 0, 1, 0xad }, { 0, 1, 0x04 } }"
register "spi.ops" = "{{0x01, WRITE_NO_ADDR},
{0x02, WRITE_WITH_ADDR},
{0x03, READ_WITH_ADDR},
{0x05, READ_NO_ADDR},
{0x20, WRITE_WITH_ADDR},
{0x9f, READ_NO_ADDR},
{0xad, WRITE_NO_ADDR},
{0x04, WRITE_NO_ADDR}}"
device pci 16.0 on # Management Engine Interface 1
subsystemid 0x174b 0x1007
end

10
src/southbridge/intel/bd82x6x/chip.h
View File

@ -16,6 +16,7 @@
#ifndef SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H
#define SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H
#include <southbridge/intel/common/spi.h>
#include <stdint.h>
struct southbridge_intel_bd82x6x_config {
@ -96,14 +97,7 @@ struct southbridge_intel_bd82x6x_config {
uint32_t spi_uvscc;
uint32_t spi_lvscc;
struct {
uint8_t opprefixes[2];
struct {
uint8_t needs_address;
uint8_t is_write;
uint8_t op;
} ops[8];
} spi;
struct intel_swseq_spi_config spi;
};
#endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */

46
src/southbridge/intel/bd82x6x/lpc.c
View File

@ -39,6 +39,7 @@
#include <southbridge/intel/common/acpi_pirq_gen.h>
#include <southbridge/intel/common/pmutil.h>
#include <southbridge/intel/common/rtc.h>
#include <southbridge/intel/common/spi.h>
#define NMI_OFF 0
@ -874,33 +875,7 @@ static void southbridge_fill_ssdt(struct device *device)
static void lpc_final(struct device *dev)
{
u16 spi_opprefix = SPI_OPPREFIX;
u16 spi_optype = SPI_OPTYPE;
u32 spi_opmenu[2] = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER };
/* Configure SPI opcode menu; devicetree may override defaults. */
const config_t *const config = dev->chip_info;
if (config && config->spi.ops[0].op) {
unsigned int i;
spi_opprefix = 0;
spi_optype = 0;
spi_opmenu[0] = 0;
spi_opmenu[1] = 0;
for (i = 0; i < sizeof(spi_opprefix); ++i)
spi_opprefix |= config->spi.opprefixes[i] << i * 8;
for (i = 0; i < sizeof(spi_opmenu); ++i) {
spi_optype |=
config->spi.ops[i].is_write << 2 * i |
config->spi.ops[i].needs_address << (2 * i + 1);
spi_opmenu[i / 4] |=
config->spi.ops[i].op << (i % 4) * 8;
}
}
RCBA16(0x3894) = spi_opprefix;
RCBA16(0x3896) = spi_optype;
RCBA32(0x3898) = spi_opmenu[0];
RCBA32(0x389c) = spi_opmenu[1];
spi_finalize_ops();
/* Call SMM finalize() handlers before resume */
if (CONFIG(HAVE_SMI_HANDLER)) {
@ -911,6 +886,23 @@ static void lpc_final(struct device *dev)
}
}
void intel_southbridge_override_spi(
struct intel_swseq_spi_config *spi_config)
{
struct device *dev = pcidev_on_root(0x1f, 0);
if (!dev)
return;
/* Devicetree may override defaults. */
const config_t *const config = dev->chip_info;
if (!config)
return;
if (config->spi.ops[0].op != 0)
memcpy(spi_config, &config->spi, sizeof(*spi_config));
}
static struct pci_operations pci_ops = {
.set_subsystem = pci_dev_set_subsystem,
};

41
src/southbridge/intel/bd82x6x/pch.h
View File

@ -561,47 +561,6 @@ void early_usb_init(const struct southbridge_usb_port *portmap);
#define TCO_LOCK (1 << 12)
#define TCO2_CNT 0x6a
/*
* SPI Opcode Menu setup for SPIBAR lockdown
* should support most common flash chips.
*/
#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
#define SPI_OPTYPE_0 0x01 /* Write, no address */
#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
#define SPI_OPTYPE_1 0x03 /* Write, address required */
#define SPI_OPMENU_2 0x03 /* READ: Read Data */
#define SPI_OPTYPE_2 0x02 /* Read, address required */
#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
#define SPI_OPTYPE_3 0x00 /* Read, no address */
#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
#define SPI_OPTYPE_4 0x03 /* Write, address required */
#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
#define SPI_OPTYPE_5 0x00 /* Read, no address */
#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
#define SPI_OPTYPE_6 0x03 /* Write, address required */
#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
#define SPI_OPTYPE_7 0x02 /* Read, address required */
#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
(SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
(SPI_OPMENU_1 << 8) | SPI_OPMENU_0)
#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
(SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
(SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
(SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
#define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */
#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */
#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */