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nb/intel/haswell/early_init.c: Remove invalid register writes 

MRC does not use the value of SSKPD, and will overwrite it with constant
values at the end of memory initialisation. Since coreboot does not rely
on this particular bit's value, it is safe to drop the writes to set it.

MCHBAR register 0x6120 is undocumented. It is nowhere to be found in any
documentation or code I have access to; not even for Sandy/Ivy Bridge,
the platform where this mysterious register write originally came from.

These workarounds were copied from Sandy Bridge, but do not apply to
Haswell. They were dropped on Broadwell, so drop them for Haswell too.

Tested on Asrock B85M Pro4, still boots.

Change-Id: I21d9656a7595d47ac8648c08d223b7cbafd213c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46683
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-10-23 11:24:07 +02:00
parent f27662f5ba
commit ebf800c538
1 changed files with 0 additions and 10 deletions
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10
src/northbridge/intel/haswell/early_init.c
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@ -146,16 +146,6 @@ static void haswell_setup_misc(void)
reg32 = MCHBAR32(SAPMCTL);
MCHBAR32(SAPMCTL) = reg32 | 1;
/* GPU RC6 workaround for sighting 366252 */
reg32 = MCHBAR32(SSKPD + 4);
reg32 |= (1UL << 31);
MCHBAR32(SSKPD + 4) = reg32;
/* VLW (Virtual Legacy Wire?) */
reg32 = MCHBAR32(0x6120);
reg32 &= ~(1 << 0);
MCHBAR32(0x6120) = reg32;
reg32 = MCHBAR32(INTRDIRCTL);
reg32 |= (1 << 4) | (1 << 5);
MCHBAR32(INTRDIRCTL) = reg32;