From ebfee7e9914770b126ba8451ef824d763e1c66c5 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 27 Aug 2014 10:28:49 -0500 Subject: [PATCH] tegra132: implement smp_processor_id() Implement smp_processor_id() for the arm64 cores. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built. Change-Id: Id2fca068f92cdc816b02b5e7ce1229517787684a Signed-off-by: Patrick Georgi Original-Commit-Id: d5c5c68329631ce0fc3cebef1c2422aa44ac192d Original-Change-Id: I7a1cd2f94ba4ae1854450cc60ef8a62f2457aabb Original-Signed-off-by: Aaron Durbin Original-Reviewed-on: https://chromium-review.googlesource.com/214664 Original-Reviewed-by: Furquan Shaikh Reviewed-on: http://review.coreboot.org/9008 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/nvidia/tegra132/Makefile.inc | 1 + src/soc/nvidia/tegra132/cpu_lib.S | 27 +++++++++++++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 src/soc/nvidia/tegra132/cpu_lib.S diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index 96961c8027..447963970c 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -52,6 +52,7 @@ ramstage-y += addressmap.c ramstage-y += cbfs.c ramstage-y += cbmem.c ramstage-y += cpu.c +ramstage-y += cpu_lib.S ramstage-y += timer.c ramstage-y += clock.c ramstage-y += soc.c diff --git a/src/soc/nvidia/tegra132/cpu_lib.S b/src/soc/nvidia/tegra132/cpu_lib.S new file mode 100644 index 0000000000..6d458d3ab7 --- /dev/null +++ b/src/soc/nvidia/tegra132/cpu_lib.S @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +.text +.global smp_processor_id +smp_processor_id: + /* Core 0 and 1 are encoded in the Aff0 (7:0) field of MPIDR_EL1. */ + mrs x0, mpidr_el1 + uxtb w0, w0 + ret