From ec0551c6b061d0bef1f9a8ec3027f7eabd088cbb Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Thu, 16 Jul 2020 22:02:43 +0300 Subject: [PATCH] util/inteltool: add missing L0 and L1 pads for Lewisburg The description for L0 and L1 was missed in the datasheet, however, configuration registers for these pads are present. In addition, the chipset contains the "GPP_L0/CSME_INTR_IN" and "GPP_L1/CSME_INTR_OUT" pads in a circuit diagram. Use all available information to add a description for the missed pads. Change-Id: I7a0488c26b3df9de1adc037d94ae290837d65dd8 Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/40044 Reviewed-by: Andrey Petrov Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- util/inteltool/gpio_names/lewisburg.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/util/inteltool/gpio_names/lewisburg.h b/util/inteltool/gpio_names/lewisburg.h index 4d5917798b..e963cc0ac8 100644 --- a/util/inteltool/gpio_names/lewisburg.h +++ b/util/inteltool/gpio_names/lewisburg.h @@ -249,6 +249,13 @@ static const char *const lewisburg_group_k_names[] = { }; static const char *const lewisburg_group_l_names[] = { + /* + * The description for L0 and L1 was missed in the datasheet, however, the chipset + * contains the GPP_L0/CSME_INTR_IN and GPP_L1/CSME_INTR_OUT pads in a schematic + * diagram and configuration registers for these pads are present. + */ + "GPP_L0", "CSME_INTR_IN", "n/a", "n/a", + "GPP_L1", "CSME_INTR_OUT", "n/a", "n/a", "GPP_L2", "TESTCH0_D0", "n/a", "n/a", "GPP_L3", "TESTCH0_D1", "n/a", "n/a", "GPP_L4", "TESTCH0_D2", "n/a", "n/a",