Clean up some #ifdef CONFIG_*
Change HAVE_FAN_CTL to be specific to the SuperIO that supports it. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
parent
a29ad5cb09
commit
ec0ee64da7
src
arch/i386/boot
config
cpu/x86/mtrr
mainboard/gigabyte/m57sli
northbridge
southbridge/via/vt8237r
superio/ite/it8716f
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@ -99,7 +99,7 @@ static struct lb_memory *lb_memory(struct lb_header *header)
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static struct lb_serial *lb_serial(struct lb_header *header)
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{
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#if defined(CONFIG_TTYS0_BASE)
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#if CONFIG_CONSOLE_SERIAL8250
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struct lb_record *rec;
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struct lb_serial *serial;
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rec = lb_new_record(header);
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@ -126,22 +126,22 @@ static void add_console(struct lb_header *header, u16 consoletype)
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static void lb_console(struct lb_header *header)
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{
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#ifdef CONFIG_CONSOLE_SERIAL8250
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#if CONFIG_CONSOLE_SERIAL8250
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add_console(header, LB_TAG_CONSOLE_SERIAL8250);
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#endif
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#ifdef CONFIG_CONSOLE_VGA
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#if CONFIG_CONSOLE_VGA
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add_console(header, LB_TAG_CONSOLE_VGA);
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#endif
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#ifdef CONFIG_CONSOLE_BTEXT
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#if CONFIG_CONSOLE_BTEXT
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add_console(header, LB_TAG_CONSOLE_BTEXT);
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#endif
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#ifdef CONFIG_CONSOLE_LOGBUF
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#if CONFIG_CONSOLE_LOGBUF
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add_console(header, LB_TAG_CONSOLE_LOGBUF);
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#endif
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#ifdef CONFIG_CONSOLE_SROM
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#if CONFIG_CONSOLE_SROM
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add_console(header, LB_TAG_CONSOLE_SROM);
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#endif
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#ifdef CONFIG_USBDEBUG_DIRECT
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#if CONFIG_USBDEBUG_DIRECT
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add_console(header, LB_TAG_CONSOLE_EHCI);
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#endif
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}
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@ -712,8 +712,8 @@ define CONFIG_PCIBIOS_IRQ
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comment "PCIBIOS IRQ support"
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end
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define CONFIG_IOAPIC
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default none
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export used
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default 0
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export always
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comment "IOAPIC support"
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end
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@ -845,7 +845,7 @@ end
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# Misc device options
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###############################################
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define CONFIG_HAVE_FANCTL
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define CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
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default 0
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export used
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comment "Include board specific FAN control initialization"
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@ -1103,14 +1103,14 @@ define CONFIG_K8_MEM_BANK_B_ONLY
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end
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define CONFIG_VIDEO_MB
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default none
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export used
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default 0
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export always
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comment "Integrated graphics with UMA has dynamic setup"
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end
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define CONFIG_GFXUMA
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default none
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export used
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default 0
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export always
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comment "GFX UMA"
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end
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@ -37,7 +37,7 @@
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/cache.h>
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#ifdef CONFIG_GFXUMA
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#if CONFIG_GFXUMA
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extern uint64_t uma_memory_base, uma_memory_size;
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#endif
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@ -150,7 +150,7 @@ else
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end
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end
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if CONFIG_HAVE_FANCTL
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if CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
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object fanctl.o
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end
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@ -7,6 +7,7 @@ config BOARD_GIGABYTE_M57SLI
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select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
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select SOUTHBRIDGE_NVIDIA_MCP55
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select SUPERIO_ITE_IT8716F
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select SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select USE_PRINTK_IN_CAR
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@ -143,9 +144,3 @@ config IRQ_SLOT_COUNT
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int
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default 11
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depends on BOARD_GIGABYTE_M57SLI
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# not globally defined yet, so can't "select" this
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config HAVE_FANCTL
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bool
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default y
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depends on BOARD_GIGABYTE_M57SLI
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@ -29,7 +29,7 @@ obj-$(CONFIG_USE_INIT) += cache_as_ram_auto.o
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obj-$(CONFIG_AP_CODE_IN_CAR) += apc_auto.o
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obj-$(CONFIG_GENERATE_ACPI_TABLES) += dsdt.o
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obj-$(CONFIG_GENERATE_ACPI_TABLES) += acpi_tables.o
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obj-$(CONFIG_HAVE_FANCTL) += fanctl.o
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obj-$(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) += fanctl.o
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# This is part of the conversion to init-obj and away from included code.
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initobj-y += crt0.o
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@ -115,7 +115,7 @@ uses CONFIG_WAIT_BEFORE_CPUS_INIT
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uses CONFIG_USE_PRINTK_IN_CAR
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uses CONFIG_HAVE_FANCTL
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uses CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
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###
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### Build options
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###
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@ -141,7 +141,7 @@ default CONFIG_RAMTOP=2048*1024
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##
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## Set-up automatic fan control
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##
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default CONFIG_HAVE_FANCTL=1
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default CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL=1
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##
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## Build code for the fallback boot
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@ -357,7 +357,7 @@ static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
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resource->gran = log2(HT_MEM_HOST_ALIGN);
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resource->limit = 0xffffffffffULL;
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resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
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#ifdef CONFIG_PCI_64BIT_PREF_MEM
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#if CONFIG_PCI_64BIT_PREF_MEM
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resource->flags |= IORESOURCE_BRIDGE;
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#endif
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}
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@ -147,7 +147,7 @@ static void pci_domain_set_resources(device_t dev)
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/* Convert tomk from MB to KB. */
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tomk = tomk << 10;
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#ifdef CONFIG_VIDEO_MB
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#if CONFIG_VIDEO_MB
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/* Check for VGA reserved memory. */
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if (CONFIG_VIDEO_MB == 512) {
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tomk -= 512;
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@ -371,7 +371,7 @@ static void sdram_set_registers(void)
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/* Set size for onboard-VGA framebuffer. */
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reg8 = pci_read_config8(PCI_DEV(0, 0, 0), SMRAM);
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reg8 &= 0x3f; /* Disable graphics (for now). */
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#ifdef CONFIG_VIDEO_MB
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#if CONFIG_VIDEO_MB
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if (CONFIG_VIDEO_MB == 512)
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reg8 |= (1 << 7); /* Enable graphics (512KB RAM). */
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else if (CONFIG_VIDEO_MB == 1)
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@ -37,7 +37,7 @@
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#define HPET_ADDR 0xfe800000UL
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#define IOAPIC_ADDR 0xfec00000ULL
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#ifdef CONFIG_IOAPIC
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#if CONFIG_IOAPIC
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struct ioapicreg {
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unsigned int reg;
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unsigned int value_low, value_high;
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@ -368,7 +368,7 @@ static void cx700_lpc_init(struct device *dev)
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{
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cx700_set_lpc_registers(dev);
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#ifdef CONFIG_IOAPIC
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#if CONFIG_IOAPIC
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setup_ioapic();
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#endif
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@ -97,7 +97,7 @@ static void ide_init(struct device *dev)
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(sb->ide1_80pin_cable << 4);
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pci_write_config32(dev, IDE_UDMA, cablesel);
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#ifdef CONFIG_EPIA_VT8237R_INIT
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#if CONFIG_EPIA_VT8237R_INIT
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/* Set PATA Output Drive Strength */
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lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
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PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
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@ -51,7 +51,7 @@
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extern void dump_south(device_t dev);
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static void southbridge_init_common(struct device *dev);
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#ifdef CONFIG_EPIA_VT8237R_INIT
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#if CONFIG_EPIA_VT8237R_INIT
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/* Interrupts for INT# A B C D */
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static const unsigned char pciIrqs[4] = { 10, 11, 12, 0};
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@ -119,7 +119,7 @@ static void setup_ioapic(u32 ioapic_base)
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ioapic_table[0].value_high = (lapicid()) << (56 - 32);
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l = (u32 *)ioapic_base;
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#ifdef CONFIG_EPIA_VT8237R_INIT
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#if CONFIG_EPIA_VT8237R_INIT
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/* Set APIC to APIC Serial bus. */
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l[0] = 0x3;
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l[4] = 0;
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@ -157,7 +157,7 @@ static void setup_ioapic(u32 ioapic_base)
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/** Set up PCI IRQ routing, route everything through APIC. */
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static void pci_routing_fixup(struct device *dev)
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{
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#ifdef CONFIG_EPIA_VT8237R_INIT
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#if CONFIG_EPIA_VT8237R_INIT
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device_t pdev;
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u8 reg;
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#endif
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@ -171,7 +171,7 @@ static void pci_routing_fixup(struct device *dev)
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/* Gate Interrupts until RAM Writes are flushed */
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pci_write_config8(dev, 0x49, 0x20);
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#ifdef CONFIG_EPIA_VT8237R_INIT
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#if CONFIG_EPIA_VT8237R_INIT
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/* Share INTE-INTH with INTA-INTD as per stock BIOS. */
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pci_write_config8(dev, 0x46, 0x00);
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@ -256,7 +256,7 @@ static void setup_pm(device_t dev)
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/* Set ACPI to 9, must set IRQ 9 override to level! Set PSON gating. */
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pci_write_config8(dev, 0x82, 0x40 | VT8237R_ACPI_IRQ);
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#ifdef CONFIG_EPIA_VT8237R_INIT
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#if CONFIG_EPIA_VT8237R_INIT
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/* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */
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pci_write_config16(dev, 0x84, 0x3052);
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#else
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@ -288,7 +288,7 @@ static void setup_pm(device_t dev)
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* 0 = USB Wakeup
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*/
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#ifdef CONFIG_EPIA_VT8237R_INIT
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#if CONFIG_EPIA_VT8237R_INIT
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pci_write_config8(dev, 0x95, 0xc2);
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#else
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pci_write_config8(dev, 0x95, 0xcc);
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@ -343,7 +343,7 @@ static void vt8237r_init(struct device *dev)
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{
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u8 enables, reg8;
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#ifdef CONFIG_EPIA_VT8237R_INIT
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#if CONFIG_EPIA_VT8237R_INIT
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printk_spew("Entering vt8237r_init, for EPIA.\n");
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/*
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* TODO: Looks like stock BIOS can do this but causes a hang
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@ -386,7 +386,7 @@ static void vt8237r_init(struct device *dev)
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enables |= 0x08;
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pci_write_config8(dev, 0x4f, enables);
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#ifdef CONFIG_EPIA_VT8237R_INIT
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#if CONFIG_EPIA_VT8237R_INIT
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/*
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* Set Read Pass Write Control Enable
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*/
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@ -401,7 +401,7 @@ static void vt8237r_init(struct device *dev)
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southbridge_init_common(dev);
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#ifndef CONFIG_EPIA_VT8237R_INIT
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#if !CONFIG_EPIA_VT8237R_INIT
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/* FIXME: Intel needs more bit set for C2/C3. */
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/*
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@ -460,7 +460,7 @@ static void vt8237_common_init(struct device *dev)
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pci_write_config8(dev, PCI_COMMAND, byte);
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/* EPIA-N(L) Uses CN400 for BIOS Access */
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#ifndef CONFIG_EPIA_VT8237R_INIT
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#if !CONFIG_EPIA_VT8237R_INIT
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/* Enable the internal I/O decode. */
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enables = pci_read_config8(dev, 0x6C);
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enables |= 0x80;
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@ -499,7 +499,7 @@ static void vt8237_common_init(struct device *dev)
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/* Delay transaction control */
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pci_write_config8(dev, 0x43, 0xb);
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#ifdef CONFIG_EPIA_VT8237R_INIT
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#if CONFIG_EPIA_VT8237R_INIT
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/* I/O recovery time, default IDE routing */
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pci_write_config8(dev, 0x4c, 0x04);
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@ -27,7 +27,7 @@
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static void vt8237_eth_read_resources(struct device *dev)
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{
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#ifdef CONFIG_EPIA_VT8237R_INIT
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#if CONFIG_EPIA_VT8237R_INIT
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struct resource *res;
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/* Fix the I/O Resources of the USB2.0 Interface */
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@ -24,14 +24,14 @@
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#include <device/pci_ids.h>
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#include "vt8237r.h"
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#ifdef CONFIG_EPIA_VT8237R_INIT
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#if CONFIG_EPIA_VT8237R_INIT
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u32 usb_io_addr[4] = {0xcc00, 0xd000, 0xd400, 0xd800};
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#endif
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static void usb_i_init(struct device *dev)
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{
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#ifdef CONFIG_EPIA_VT8237R_INIT
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#if CONFIG_EPIA_VT8237R_INIT
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u8 reg8;
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printk_debug("Entering %s\n", __func__);
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static void vt8237_usb_i_read_resources(struct device *dev)
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{
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#ifdef CONFIG_EPIA_VT8237R_INIT
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#if CONFIG_EPIA_VT8237R_INIT
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struct resource *res;
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u8 function = (u8) dev->path.pci.devfn & 0x7;
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@ -95,7 +95,7 @@ static void vt8237_usb_i_read_resources(struct device *dev)
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static void usb_ii_init(struct device *dev)
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{
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#ifdef CONFIG_EPIA_VT8237R_INIT
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#if CONFIG_EPIA_VT8237R_INIT
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u8 reg8;
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printk_debug("Entering %s\n", __func__);
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@ -117,7 +117,7 @@ static void usb_ii_init(struct device *dev)
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static void vt8237_usb_ii_read_resources(struct device *dev)
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{
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#ifdef CONFIG_EPIA_VT8237R_INIT
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#if CONFIG_EPIA_VT8237R_INIT
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struct resource *res;
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/* Fix the I/O Resources of the USB2.0 Interface */
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@ -51,7 +51,7 @@ static void pnp_exit_ext_func_mode(device_t dev)
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pnp_write_config(dev, 0x02, 0x02);
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}
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#ifdef CONFIG_HAVE_FANCTL
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#if CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
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extern void init_ec(uint16_t base);
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#else
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static void pnp_write_index(uint16_t port_base, uint8_t reg, uint8_t value)
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