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Clean up some #ifdef CONFIG_* 

Change HAVE_FAN_CTL to be specific to the SuperIO that supports it.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson 2009-10-19 16:21:30 +00:00
parent a29ad5cb09
commit ec0ee64da7
16 changed files with 44 additions and 49 deletions
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14
src/arch/i386/boot/coreboot_table.c
View File

@ -99,7 +99,7 @@ static struct lb_memory *lb_memory(struct lb_header *header)
static struct lb_serial *lb_serial(struct lb_header *header)
{
#if defined(CONFIG_TTYS0_BASE)
#if CONFIG_CONSOLE_SERIAL8250
struct lb_record *rec;
struct lb_serial *serial;
rec = lb_new_record(header);
@ -126,22 +126,22 @@ static void add_console(struct lb_header *header, u16 consoletype)
static void lb_console(struct lb_header *header)
{
#ifdef CONFIG_CONSOLE_SERIAL8250
#if CONFIG_CONSOLE_SERIAL8250
add_console(header, LB_TAG_CONSOLE_SERIAL8250);
#endif
#ifdef CONFIG_CONSOLE_VGA
#if CONFIG_CONSOLE_VGA
add_console(header, LB_TAG_CONSOLE_VGA);
#endif
#ifdef CONFIG_CONSOLE_BTEXT
#if CONFIG_CONSOLE_BTEXT
add_console(header, LB_TAG_CONSOLE_BTEXT);
#endif
#ifdef CONFIG_CONSOLE_LOGBUF
#if CONFIG_CONSOLE_LOGBUF
add_console(header, LB_TAG_CONSOLE_LOGBUF);
#endif
#ifdef CONFIG_CONSOLE_SROM
#if CONFIG_CONSOLE_SROM
add_console(header, LB_TAG_CONSOLE_SROM);
#endif
#ifdef CONFIG_USBDEBUG_DIRECT
#if CONFIG_USBDEBUG_DIRECT
add_console(header, LB_TAG_CONSOLE_EHCI);
#endif
}

14
src/config/Options.lb
View File

@ -712,8 +712,8 @@ define CONFIG_PCIBIOS_IRQ
comment "PCIBIOS IRQ support"
end
define CONFIG_IOAPIC
default none
export used
default 0
export always
comment "IOAPIC support"
end
@ -845,7 +845,7 @@ end
# Misc device options
###############################################
define CONFIG_HAVE_FANCTL
define CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
default 0
export used
comment "Include board specific FAN control initialization"
@ -1103,14 +1103,14 @@ define CONFIG_K8_MEM_BANK_B_ONLY
end
define CONFIG_VIDEO_MB
default none
export used
default 0
export always
comment "Integrated graphics with UMA has dynamic setup"
end
define CONFIG_GFXUMA
default none
export used
default 0
export always
comment "GFX UMA"
end

2
src/cpu/x86/mtrr/mtrr.c
View File

@ -37,7 +37,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#ifdef CONFIG_GFXUMA
#if CONFIG_GFXUMA
extern uint64_t uma_memory_base, uma_memory_size;
#endif

2
src/mainboard/gigabyte/m57sli/Config.lb
View File

@ -150,7 +150,7 @@ else
end
end
if CONFIG_HAVE_FANCTL
if CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
object fanctl.o
end

7
src/mainboard/gigabyte/m57sli/Kconfig
View File

@ -7,6 +7,7 @@ config BOARD_GIGABYTE_M57SLI
select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
select SOUTHBRIDGE_NVIDIA_MCP55
select SUPERIO_ITE_IT8716F
select SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_PRINTK_IN_CAR
@ -143,9 +144,3 @@ config IRQ_SLOT_COUNT
int
default 11
depends on BOARD_GIGABYTE_M57SLI
# not globally defined yet, so can't "select" this
config HAVE_FANCTL
bool
default y
depends on BOARD_GIGABYTE_M57SLI

2
src/mainboard/gigabyte/m57sli/Makefile.inc
View File

@ -29,7 +29,7 @@ obj-$(CONFIG_USE_INIT) += cache_as_ram_auto.o
obj-$(CONFIG_AP_CODE_IN_CAR) += apc_auto.o
obj-$(CONFIG_GENERATE_ACPI_TABLES) += dsdt.o
obj-$(CONFIG_GENERATE_ACPI_TABLES) += acpi_tables.o
obj-$(CONFIG_HAVE_FANCTL) += fanctl.o
obj-$(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) += fanctl.o
# This is part of the conversion to init-obj and away from included code.
initobj-y += crt0.o

4
src/mainboard/gigabyte/m57sli/Options.lb
View File

@ -115,7 +115,7 @@ uses CONFIG_WAIT_BEFORE_CPUS_INIT
uses CONFIG_USE_PRINTK_IN_CAR
uses CONFIG_HAVE_FANCTL
uses CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
###
### Build options
###
@ -141,7 +141,7 @@ default CONFIG_RAMTOP=2048*1024
##
## Set-up automatic fan control
##
default CONFIG_HAVE_FANCTL=1
default CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL=1
##
## Build code for the fallback boot

2
src/northbridge/amd/amdk8/northbridge.c
View File

@ -357,7 +357,7 @@ static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
resource->gran = log2(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
#ifdef CONFIG_PCI_64BIT_PREF_MEM
#if CONFIG_PCI_64BIT_PREF_MEM
resource->flags |= IORESOURCE_BRIDGE;
#endif
}

2
src/northbridge/intel/i82810/northbridge.c
View File

@ -147,7 +147,7 @@ static void pci_domain_set_resources(device_t dev)
/* Convert tomk from MB to KB. */
tomk = tomk << 10;
#ifdef CONFIG_VIDEO_MB
#if CONFIG_VIDEO_MB
/* Check for VGA reserved memory. */
if (CONFIG_VIDEO_MB == 512) {
tomk -= 512;

2
src/northbridge/intel/i82810/raminit.c
View File

@ -371,7 +371,7 @@ static void sdram_set_registers(void)
/* Set size for onboard-VGA framebuffer. */
reg8 = pci_read_config8(PCI_DEV(0, 0, 0), SMRAM);
reg8 &= 0x3f; /* Disable graphics (for now). */
#ifdef CONFIG_VIDEO_MB
#if CONFIG_VIDEO_MB
if (CONFIG_VIDEO_MB == 512)
reg8 |= (1 << 7); /* Enable graphics (512KB RAM). */
else if (CONFIG_VIDEO_MB == 1)

4
src/northbridge/via/cx700/cx700_lpc.c
View File

@ -37,7 +37,7 @@
#define HPET_ADDR 0xfe800000UL
#define IOAPIC_ADDR 0xfec00000ULL
#ifdef CONFIG_IOAPIC
#if CONFIG_IOAPIC
struct ioapicreg {
unsigned int reg;
unsigned int value_low, value_high;
@ -368,7 +368,7 @@ static void cx700_lpc_init(struct device *dev)
{
cx700_set_lpc_registers(dev);
#ifdef CONFIG_IOAPIC
#if CONFIG_IOAPIC
setup_ioapic();
#endif

2
src/southbridge/via/vt8237r/vt8237r_ide.c
View File

@ -97,7 +97,7 @@ static void ide_init(struct device *dev)
(sb->ide1_80pin_cable << 4);
pci_write_config32(dev, IDE_UDMA, cablesel);
#ifdef CONFIG_EPIA_VT8237R_INIT
#if CONFIG_EPIA_VT8237R_INIT
/* Set PATA Output Drive Strength */
lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);

22
src/southbridge/via/vt8237r/vt8237r_lpc.c
View File

@ -51,7 +51,7 @@
extern void dump_south(device_t dev);
static void southbridge_init_common(struct device *dev);
#ifdef CONFIG_EPIA_VT8237R_INIT
#if CONFIG_EPIA_VT8237R_INIT
/* Interrupts for INT# A B C D */
static const unsigned char pciIrqs[4] = { 10, 11, 12, 0};
@ -119,7 +119,7 @@ static void setup_ioapic(u32 ioapic_base)
ioapic_table[0].value_high = (lapicid()) << (56 - 32);
l = (u32 *)ioapic_base;
#ifdef CONFIG_EPIA_VT8237R_INIT
#if CONFIG_EPIA_VT8237R_INIT
/* Set APIC to APIC Serial bus. */
l[0] = 0x3;
l[4] = 0;
@ -157,7 +157,7 @@ static void setup_ioapic(u32 ioapic_base)
/** Set up PCI IRQ routing, route everything through APIC. */
static void pci_routing_fixup(struct device *dev)
{
#ifdef CONFIG_EPIA_VT8237R_INIT
#if CONFIG_EPIA_VT8237R_INIT
device_t pdev;
u8 reg;
#endif
@ -171,7 +171,7 @@ static void pci_routing_fixup(struct device *dev)
/* Gate Interrupts until RAM Writes are flushed */
pci_write_config8(dev, 0x49, 0x20);
#ifdef CONFIG_EPIA_VT8237R_INIT
#if CONFIG_EPIA_VT8237R_INIT
/* Share INTE-INTH with INTA-INTD as per stock BIOS. */
pci_write_config8(dev, 0x46, 0x00);
@ -256,7 +256,7 @@ static void setup_pm(device_t dev)
/* Set ACPI to 9, must set IRQ 9 override to level! Set PSON gating. */
pci_write_config8(dev, 0x82, 0x40 | VT8237R_ACPI_IRQ);
#ifdef CONFIG_EPIA_VT8237R_INIT
#if CONFIG_EPIA_VT8237R_INIT
/* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */
pci_write_config16(dev, 0x84, 0x3052);
#else
@ -288,7 +288,7 @@ static void setup_pm(device_t dev)
* 0 = USB Wakeup
*/
#ifdef CONFIG_EPIA_VT8237R_INIT
#if CONFIG_EPIA_VT8237R_INIT
pci_write_config8(dev, 0x95, 0xc2);
#else
pci_write_config8(dev, 0x95, 0xcc);
@ -343,7 +343,7 @@ static void vt8237r_init(struct device *dev)
{
u8 enables, reg8;
#ifdef CONFIG_EPIA_VT8237R_INIT
#if CONFIG_EPIA_VT8237R_INIT
printk_spew("Entering vt8237r_init, for EPIA.\n");
/*
* TODO: Looks like stock BIOS can do this but causes a hang
@ -386,7 +386,7 @@ static void vt8237r_init(struct device *dev)
enables |= 0x08;
pci_write_config8(dev, 0x4f, enables);
#ifdef CONFIG_EPIA_VT8237R_INIT
#if CONFIG_EPIA_VT8237R_INIT
/*
* Set Read Pass Write Control Enable
*/
@ -401,7 +401,7 @@ static void vt8237r_init(struct device *dev)
southbridge_init_common(dev);
#ifndef CONFIG_EPIA_VT8237R_INIT
#if !CONFIG_EPIA_VT8237R_INIT
/* FIXME: Intel needs more bit set for C2/C3. */
/*
@ -460,7 +460,7 @@ static void vt8237_common_init(struct device *dev)
pci_write_config8(dev, PCI_COMMAND, byte);
/* EPIA-N(L) Uses CN400 for BIOS Access */
#ifndef CONFIG_EPIA_VT8237R_INIT
#if !CONFIG_EPIA_VT8237R_INIT
/* Enable the internal I/O decode. */
enables = pci_read_config8(dev, 0x6C);
enables |= 0x80;
@ -499,7 +499,7 @@ static void vt8237_common_init(struct device *dev)
/* Delay transaction control */
pci_write_config8(dev, 0x43, 0xb);
#ifdef CONFIG_EPIA_VT8237R_INIT
#if CONFIG_EPIA_VT8237R_INIT
/* I/O recovery time, default IDE routing */
pci_write_config8(dev, 0x4c, 0x04);

2
src/southbridge/via/vt8237r/vt8237r_nic.c
View File

@ -27,7 +27,7 @@
static void vt8237_eth_read_resources(struct device *dev)
{
#ifdef CONFIG_EPIA_VT8237R_INIT
#if CONFIG_EPIA_VT8237R_INIT
struct resource *res;
/* Fix the I/O Resources of the USB2.0 Interface */

10
src/southbridge/via/vt8237r/vt8237r_usb.c
View File

@ -24,14 +24,14 @@
#include <device/pci_ids.h>
#include "vt8237r.h"
#ifdef CONFIG_EPIA_VT8237R_INIT
#if CONFIG_EPIA_VT8237R_INIT
u32 usb_io_addr[4] = {0xcc00, 0xd000, 0xd400, 0xd800};
#endif
static void usb_i_init(struct device *dev)
{
#ifdef CONFIG_EPIA_VT8237R_INIT
#if CONFIG_EPIA_VT8237R_INIT
u8 reg8;
printk_debug("Entering %s\n", __func__);
@ -70,7 +70,7 @@ static void usb_i_init(struct device *dev)
static void vt8237_usb_i_read_resources(struct device *dev)
{
#ifdef CONFIG_EPIA_VT8237R_INIT
#if CONFIG_EPIA_VT8237R_INIT
struct resource *res;
u8 function = (u8) dev->path.pci.devfn & 0x7;
@ -95,7 +95,7 @@ static void vt8237_usb_i_read_resources(struct device *dev)
static void usb_ii_init(struct device *dev)
{
#ifdef CONFIG_EPIA_VT8237R_INIT
#if CONFIG_EPIA_VT8237R_INIT
u8 reg8;
printk_debug("Entering %s\n", __func__);
@ -117,7 +117,7 @@ static void usb_ii_init(struct device *dev)
static void vt8237_usb_ii_read_resources(struct device *dev)
{
#ifdef CONFIG_EPIA_VT8237R_INIT
#if CONFIG_EPIA_VT8237R_INIT
struct resource *res;
/* Fix the I/O Resources of the USB2.0 Interface */

2
src/superio/ite/it8716f/superio.c
View File

@ -51,7 +51,7 @@ static void pnp_exit_ext_func_mode(device_t dev)
pnp_write_config(dev, 0x02, 0x02);
}
#ifdef CONFIG_HAVE_FANCTL
#if CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
extern void init_ec(uint16_t base);
#else
static void pnp_write_index(uint16_t port_base, uint8_t reg, uint8_t value)