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soc/intel/cannonlake: Add PCH ID support in bootblock/report_platform.c 

This patch ensures that all required information for pch/mch/igd
deviceid and revision are available in single stage and makes
use of local references.

TEST=Build and boot cannonlake_rvp to get PCH information as below
PCH: device id xxxx (rev xx) is Cannonlake-Y Premium

Change-Id: I420e94043145e8a5adcf8bb51239657891915d84
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Subrata Banik 2017-12-07 11:48:48 +05:30
parent df5ae9ce64
commit ec10fbb90e
2 changed files with 44 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

49
src/soc/intel/cannonlake/bootblock/report_platform.c
View File

@ -45,6 +45,15 @@ static struct {
{ PCI_DEVICE_ID_INTEL_CNL_ID_Y, "Cannonlake-Y" },
};
static struct {
u16 lpcid;
const char *name;
} pch_table[] = {
{ PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC, "Cannonlake-U Base" },
{ PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC, "Cannonlake-U Premium" },
{ PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, "Cannonlake-Y Premium" },
};
static struct {
u16 igdid;
const char *name;
@ -59,6 +68,16 @@ static struct {
{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, "Cannonlake ULT GT0.5" },
};
static uint8_t get_dev_revision(device_t dev)
{
return pci_read_config8(dev, PCI_REVISION_ID);
}
static uint16_t get_dev_id(device_t dev)
{
return pci_read_config16(dev, PCI_DEVICE_ID);
}
static void report_cpu_info(void)
{
struct cpuid_result cpuidr;
@ -120,8 +139,9 @@ static void report_cpu_info(void)
static void report_mch_info(void)
{
int i;
u16 mchid = pci_read_config16(SA_DEV_ROOT, PCI_DEVICE_ID);
u8 mch_revision = pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID);
device_t dev = SA_DEV_ROOT;
uint16_t mchid = get_dev_id(dev);
uint8_t mch_revision = get_dev_revision(dev);
const char *mch_type = "Unknown";
for (i = 0; i < ARRAY_SIZE(mch_table); i++) {
@ -132,13 +152,31 @@ static void report_mch_info(void)
}
printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n",
mchid, mch_revision, mch_type);
mchid, mch_revision, mch_type);
}
static void report_pch_info(void)
{
int i;
device_t dev = PCH_DEV_LPC;
uint16_t lpcid = get_dev_id(dev);
const char *pch_type = "Unknown";
for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
if (pch_table[i].lpcid == lpcid) {
pch_type = pch_table[i].name;
break;
}
}
printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n",
lpcid, get_dev_revision(dev), pch_type);
}
static void report_igd_info(void)
{
int i;
u16 igdid = pci_read_config16(SA_DEV_IGD, PCI_DEVICE_ID);
device_t dev = SA_DEV_IGD;
uint16_t igdid = get_dev_id(dev);
const char *igd_type = "Unknown";
for (i = 0; i < ARRAY_SIZE(igd_table); i++) {
@ -148,12 +186,13 @@ static void report_igd_info(void)
}
}
printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n",
igdid, pci_read_config8(SA_DEV_IGD, PCI_REVISION_ID), igd_type);
igdid, get_dev_revision(dev), igd_type);
}
void report_platform_info(void)
{
report_cpu_info();
report_mch_info();
report_pch_info();
report_igd_info();
}

2
src/soc/intel/cannonlake/include/soc/pch.h
View File

@ -28,8 +28,6 @@
#define PCIE_CLK_LAN 0x70
#define PCIE_CLK_FREE 0x80
u8 pch_revision(void);
u16 pch_type(void);
void pch_log_state(void);
void pch_uart_init(void);