Add support for the ASUS P2B-LS mainboard.
Signed-off-by: Keith Hui <buurin@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5188 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Keith Hui
Uwe Hermann
parent
e1ec158c0a
commit
ec42c2e8ac
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@ -27,6 +27,7 @@ source "src/mainboard/asus/a8v-e_se/Kconfig"
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source "src/mainboard/asus/p2b/Kconfig"
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source "src/mainboard/asus/p2b/Kconfig"
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source "src/mainboard/asus/p2b-d/Kconfig"
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source "src/mainboard/asus/p2b-d/Kconfig"
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source "src/mainboard/asus/p2b-ds/Kconfig"
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source "src/mainboard/asus/p2b-ds/Kconfig"
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source "src/mainboard/asus/p2b-ls/Kconfig"
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source "src/mainboard/asus/p2b-f/Kconfig"
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source "src/mainboard/asus/p2b-f/Kconfig"
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source "src/mainboard/asus/p3b-f/Kconfig"
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source "src/mainboard/asus/p3b-f/Kconfig"
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source "src/mainboard/asus/m2v-mx_se/Kconfig"
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source "src/mainboard/asus/m2v-mx_se/Kconfig"
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@ -0,0 +1,52 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2010 Keith Hui <buurin@gmail.com>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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config BOARD_ASUS_P2B_LS
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bool "P2B-LS"
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select ARCH_X86
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select CPU_INTEL_SLOT_1
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select NORTHBRIDGE_INTEL_I440BX
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select SOUTHBRIDGE_INTEL_I82371EB
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select SUPERIO_WINBOND_W83977TF
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select ROMCC
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select HAVE_PIRQ_TABLE
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select UDELAY_TSC
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select BOARD_ROMSIZE_KB_256
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config MAINBOARD_DIR
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string
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default asus/p2b-ls
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depends on BOARD_ASUS_P2B_LS
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config MAINBOARD_PART_NUMBER
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string
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default "P2B-LS"
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depends on BOARD_ASUS_P2B_LS
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config HAVE_OPTION_TABLE
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bool
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default n
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depends on BOARD_ASUS_P2B_LS
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config IRQ_SLOT_COUNT
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int
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default 8
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depends on BOARD_ASUS_P2B_LS
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@ -0,0 +1,22 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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extern struct chip_operations mainboard_ops;
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struct mainboard_config {};
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@ -0,0 +1,59 @@
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chip northbridge/intel/i440bx # Northbridge
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device apic_cluster 0 on # APIC cluster
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chip cpu/intel/slot_1 # CPU
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device apic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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device pci 0.0 on end # Host bridge
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device pci 1.0 on end # PCI/AGP bridge
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chip southbridge/intel/i82371eb # Southbridge
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device pci 4.0 on # ISA bridge
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chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!)
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device pnp 3f0.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 3f0.1 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 3f0.2 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 3f0.3 on # COM2 / IR
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 3f0.5 on # PS/2 keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1 # PS/2 keyboard interrupt
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irq 0x72 = 12 # PS/2 mouse interrupt
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end
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device pnp 3f0.7 on # GPIO 1
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end
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device pnp 3f0.8 on # GPIO 2
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end
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device pnp 3f0.a on # ACPI
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end
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end
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end
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device pci 4.1 on end # IDE
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device pci 4.2 on end # USB
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device pci 4.3 on end # ACPI
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device pci 6.0 on end # Onboard SCSI
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device pci 7.0 on end # Onboard LAN
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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register "ide_legacy_enable" = "1"
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# Enable UDMA/33 for higher speed if your IDE device(s) support it.
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register "ide0_drive0_udma33_enable" = "0"
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register "ide0_drive1_udma33_enable" = "0"
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register "ide1_drive0_udma33_enable" = "0"
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register "ide1_drive1_udma33_enable" = "0"
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end
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end
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end
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@ -0,0 +1,54 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Keith Hui <buurin@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/pirq_routing.h>
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE,
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PIRQ_VERSION,
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32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
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0x00, /* Interrupt router bus */
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(0x04 << 3) | 0x0, /* Interrupt router device */
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0, /* IRQs devoted exclusively to PCI usage */
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0x8086, /* Vendor */
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0x122e, /* Device */
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0, /* Miniport */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0x10, /* Checksum (has to be set to some value that
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* would give 0 after the sum of all bytes
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* for this structure (including checksum).
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*/
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{
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/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x00, (0x0c << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x1, 0x0},
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{0x00, (0x0b << 3) | 0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}}, 0x2, 0x0},
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{0x00, (0x0a << 3) | 0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x3, 0x0},
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{0x00, (0x09 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x4, 0x0},
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{0x00, (0x04 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0},
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{0x00, (0x01 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0},
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{0x00, (0x06 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x0, 0x0},
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{0x00, (0x07 << 3) | 0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x0, 0x0},
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}
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -0,0 +1,26 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <device/device.h>
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#include "chip.h"
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struct chip_operations mainboard_ops = {
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CHIP_NAME("ASUS P2B-LS Mainboard")
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};
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@ -0,0 +1,75 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define ASSEMBLY 1
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#define __PRE_RAM__
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <arch/hlt.h>
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#include <stdlib.h>
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "lib/ramtest.c"
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#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
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#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
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#include "northbridge/intel/i440bx/raminit.h"
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#include "lib/debug.c"
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#include "pc80/udelay_io.c"
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#include "lib/delay.c"
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#include "cpu/x86/mtrr/earlymtrr.c"
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#include "cpu/x86/bist.h"
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/* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */
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#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
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#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
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static inline int spd_read_byte(unsigned int device, unsigned int address)
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{
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return smbus_read_byte(device, address);
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}
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#include "northbridge/intel/i440bx/raminit.c"
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#include "northbridge/intel/i440bx/debug.c"
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static void main(unsigned long bist)
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{
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if (bist == 0)
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early_mtrr_init();
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/* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */
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w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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uart_init();
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console_init();
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report_bist_failure(bist);
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/* Enable access to the full ROM chip, needed very early by CBFS. */
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i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */
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enable_smbus();
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/* dump_spd_registers(); */
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sdram_set_registers();
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sdram_set_spd_registers();
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sdram_enable();
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/* ram_check(0, 640 * 1024); */
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}
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