From ec7a932aa291e228d629be2d5d273fe625643588 Mon Sep 17 00:00:00 2001 From: "Chris.Wang" Date: Fri, 1 Apr 2022 14:53:39 +0800 Subject: [PATCH] mb/google/skyrim/var/baseboard: Set Clk request for WLAN/SD/SSD device Setting the clock source depends on clock request pin for WLAN/SD/SSD device. Also turn off the unused (CLKREQ#3) clock sources.In skyrim, clock source 0/1/2 are routed for WLAN/SD/SSD device. BUG=b:227297986 BRANCH=none TEST=Build Signed-off-by: Chris.Wang Change-Id: I21fb912b69f59717eb4e84c379f706a0257a9ed1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63295 Tested-by: build bot (Jenkins) Reviewed-by: Jon Murphy Reviewed-by: Felix Held --- .../google/skyrim/variants/baseboard/devicetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb index 7f74d6d6fd..a6894eefa4 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb @@ -47,6 +47,12 @@ chip soc/amd/sabrina register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" # Audio/SAR register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" # GSC + # general purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_REQ" + register "gpp_clk_config[1]" = "GPP_CLK_REQ" + register "gpp_clk_config[2]" = "GPP_CLK_REQ" + register "gpp_clk_config[3]" = "GPP_CLK_OFF" + register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works device domain 0 on