mb/google/brya/variants/*: Add cpu pcie rp flags
Along with commit f94405219c
(soc/intel/alderlake: Hook up FSP-S CPU
PCIe UPDs), we need to set cpu pcie rp flags in devicetree now.
This CL is to add proper cpu pcie flags (PCIE_RP_LTR and PCIE_RP_AER) in
all intel projects or system will be blocked at PKGC2R with root port
LTR not enable.
BUG=b:214009181
TEST=Build and DUT (Kano) can enter deeper PKGC state normally.
Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com>
Change-Id: I0d8721bf1454448b7fc14655f0e4513001469a18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
parent
c89be7ae42
commit
ec877d633d
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@ -97,6 +97,7 @@ chip soc/intel/alderlake
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register "cpu_pcie_rp[CPU_RP(1)]" = "{
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.clk_req = 0,
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.clk_src = 0,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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end
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device ref tcss_dma0 on
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@ -182,6 +182,7 @@ chip soc/intel/alderlake
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register "cpu_pcie_rp[CPU_RP(1)]" = "{
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.clk_req = 0,
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.clk_src = 0,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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end
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device ref tcss_dma0 on
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@ -228,6 +228,7 @@ chip soc/intel/alderlake
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register "cpu_pcie_rp[CPU_RP(1)]" = "{
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.clk_req = 0,
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.clk_src = 0,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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probe BOOT_NVME_MASK BOOT_NVME_ENABLED
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end
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@ -224,6 +224,7 @@ chip soc/intel/alderlake
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register "cpu_pcie_rp[CPU_RP(1)]" = "{
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.clk_req = 0,
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.clk_src = 0,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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end
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device ref tbt_pcie_rp0 off end
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@ -221,6 +221,7 @@ chip soc/intel/alderlake
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register "cpu_pcie_rp[CPU_RP(1)]" = "{
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.clk_req = 0,
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.clk_src = 0,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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end
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device ref tbt_pcie_rp0 off end
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@ -144,6 +144,7 @@ chip soc/intel/alderlake
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register "cpu_pcie_rp[CPU_RP(1)]" = "{
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.clk_req = 1,
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.clk_src = 1,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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end
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device ref cnvi_wifi on
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@ -81,18 +81,21 @@ chip soc/intel/alderlake
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register "cpu_pcie_rp[CPU_RP(1)]" = "{
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.clk_req = 0,
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.clk_src = 0,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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# Enable CPU PCIE RP 2 using CLK 3
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register "cpu_pcie_rp[CPU_RP(2)]" = "{
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.clk_req = 3,
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.clk_src = 3,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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# Enable CPU PCIE RP 3 using CLK 4
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register "cpu_pcie_rp[CPU_RP(3)]" = "{
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.clk_req = 4,
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.clk_src = 4,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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register "SataSalpSupport" = "1"
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@ -89,6 +89,7 @@ chip soc/intel/alderlake
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register "cpu_pcie_rp[CPU_RP(1)]" = "{
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.clk_req = 0,
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.clk_src = 0,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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# Enable EDP in PortA
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