mb/google/brya/variants/*: Add cpu pcie rp flags

Along with commit f94405219c (soc/intel/alderlake: Hook up FSP-S CPU
PCIe UPDs), we need to set cpu pcie rp flags in devicetree now.

This CL is to add proper cpu pcie flags (PCIE_RP_LTR and PCIE_RP_AER) in
all intel projects or system will be blocked at PKGC2R with root port
LTR not enable.

BUG=b:214009181
TEST=Build and DUT (Kano) can enter deeper PKGC state normally.

Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com>
Change-Id: I0d8721bf1454448b7fc14655f0e4513001469a18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/mainboard/google/brya/variants/brask/overridetree.cb

@@ -97,6 +97,7 @@ chip soc/intel/alderlake
 			register "cpu_pcie_rp[CPU_RP(1)]" = "{
 				.clk_req = 0,
 				.clk_src = 0,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
 		end
 		device ref tcss_dma0 on

src/mainboard/google/brya/variants/kano/overridetree.cb

@@ -182,6 +182,7 @@ chip soc/intel/alderlake
 			register "cpu_pcie_rp[CPU_RP(1)]" = "{
 				.clk_req = 0,
 				.clk_src = 0,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
 		end
 		device ref tcss_dma0 on

src/mainboard/google/brya/variants/taeko/overridetree.cb

@@ -228,6 +228,7 @@ chip soc/intel/alderlake
 			register "cpu_pcie_rp[CPU_RP(1)]" = "{
 				.clk_req = 0,
 				.clk_src = 0,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
 			probe BOOT_NVME_MASK BOOT_NVME_ENABLED
 		end

src/mainboard/google/brya/variants/taeko4es/overridetree.cb

@@ -224,6 +224,7 @@ chip soc/intel/alderlake
 			register "cpu_pcie_rp[CPU_RP(1)]" = "{
 				.clk_req = 0,
 				.clk_src = 0,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
 		end
 		device ref tbt_pcie_rp0 off end

src/mainboard/google/brya/variants/taniks/overridetree.cb

@@ -221,6 +221,7 @@ chip soc/intel/alderlake
 			register "cpu_pcie_rp[CPU_RP(1)]" = "{
 				.clk_req = 0,
 				.clk_src = 0,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
 		end
 		device ref tbt_pcie_rp0 off end

src/mainboard/google/brya/variants/vell/overridetree.cb

@@ -144,6 +144,7 @@ chip soc/intel/alderlake
 			register "cpu_pcie_rp[CPU_RP(1)]" = "{
 				.clk_req = 1,
 				.clk_src = 1,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
 		end
 		device ref cnvi_wifi on

src/mainboard/intel/adlrvp/devicetree.cb

@@ -81,18 +81,21 @@ chip soc/intel/alderlake
 	register "cpu_pcie_rp[CPU_RP(1)]" = "{
 		.clk_req = 0,
 		.clk_src = 0,
+		.flags = PCIE_RP_LTR | PCIE_RP_AER,
 	}"
 
 	# Enable CPU PCIE RP 2 using CLK 3
 	register "cpu_pcie_rp[CPU_RP(2)]" = "{
 		.clk_req = 3,
 		.clk_src = 3,
+		.flags = PCIE_RP_LTR | PCIE_RP_AER,
 	}"
 
 	# Enable CPU PCIE RP 3 using CLK 4
 	register "cpu_pcie_rp[CPU_RP(3)]" = "{
 		.clk_req = 4,
 		.clk_src = 4,
+		.flags = PCIE_RP_LTR | PCIE_RP_AER,
 	}"
 
 	register "SataSalpSupport" = "1"

src/mainboard/intel/adlrvp/devicetree_m.cb

@@ -89,6 +89,7 @@ chip soc/intel/alderlake
 	register "cpu_pcie_rp[CPU_RP(1)]" = "{
 		.clk_req = 0,
 		.clk_src = 0,
+		.flags = PCIE_RP_LTR | PCIE_RP_AER,
 	}"
 
 	# Enable EDP in PortA