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xeon_sp/cpx: Enable PCH thermal device via FSP 

Tested=On OCP Delta Lake, OpenBMC sensor-util can see PCH Temp readings.

Change-Id: I39d0d0a982476f9fece51cfa19dcbd0da5dea690
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44075
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Johnny Lin 2020-07-31 14:46:41 +08:00 committed by Angel Pons
parent f2a59a4de2
commit ec886ec6fa
2 changed files with 9 additions and 0 deletions
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2
src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
View File

@ -92,6 +92,8 @@
#define XHCI_BUS_NUMBER 0x0
#define PCH_DEV_SLOT_XHCI 0x14
#define PCH_DEVFN_THERMAL _PCH_DEVFN(XHCI, 2)
#define XHCI_FUNC_NUM 0x0
#define HPET_BUS_NUM 0x0

7
src/soc/intel/xeon_sp/cpx/romstage.c
View File

@ -3,6 +3,7 @@
#include <arch/romstage.h>
#include <fsp/api.h>
#include <soc/romstage.h>
#include <soc/pci_devs.h>
#include "chip.h"
void __weak mainboard_memory_init_params(FSPM_UPD *mupd)
@ -13,6 +14,7 @@ void __weak mainboard_memory_init_params(FSPM_UPD *mupd)
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{
FSPM_CONFIG *m_cfg = &mupd->FspmConfig;
const struct device *dev;
/* ErrorLevel - 0 (disable) to 8 (verbose) */
m_cfg->DebugPrintLevel = 8;
@ -61,5 +63,10 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
m_cfg->PEXPHIDE = 0x0;
m_cfg->HidePEXPMenu = 0x0;
/* Enable PCH thermal device in FSP, the definition of ThermalDeviceEnable is
0: Disable, 1: Enabled in PCI mode, 2: Enabled in ACPI mode */
dev = pcidev_path_on_root(PCH_DEVFN_THERMAL);
m_cfg->ThermalDeviceEnable = dev && dev->enabled;
mainboard_memory_init_params(mupd);
}