From ec953face1ef1e09bc3ebcf5513dfb03253117dc Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 19 Feb 2021 21:40:15 +0100 Subject: [PATCH] skylake,fsp1_1: Delete dead `report_memory_config()` function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit RAM is not yet configured in bootblock. This function was copy-pasted from Broadwell. Also, Skylake no longer uses FSP 1.1 and the stubs in there can be removed as nothing else uses them. Change-Id: I22cb7e63ed1e9565934296fd40771130ba91d227 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/50949 Reviewed-by: Michael Niewöhner Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- .../intel/fsp1_1/include/fsp/romstage.h | 1 - src/drivers/intel/fsp1_1/raminit.c | 3 -- src/drivers/intel/fsp1_1/romstage.c | 5 --- .../intel/skylake/bootblock/report_platform.c | 41 ------------------- src/soc/intel/skylake/include/soc/bootblock.h | 1 - 5 files changed, 51 deletions(-) diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index 23eadfa978..db4b352594 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -34,7 +34,6 @@ void mainboard_add_dimm_info(struct romstage_params *params, struct memory_info *mem_info, int channel, int dimm, int index); void raminit(struct romstage_params *params); -void report_memory_config(void); /* Initialize memory margin analysis settings. */ void setup_mma(MEMORY_INIT_UPD *memory_upd); void soc_after_ram_init(struct romstage_params *params); diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 4c468e5534..44e7693991 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -237,9 +237,6 @@ void raminit(struct romstage_params *params) die_with_post_code(POST_INVALID_VENDOR_BINARY, "ERROR - coreboot's requirements not met by FSP binary!\n"); - /* Display the memory configuration */ - report_memory_config(); - /* Locate the memory configuration data to speed up the next reboot */ mrc_hob = get_next_guid_hob(&mrc_guid, hob_list_ptr); if (mrc_hob == NULL) { diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 5129dc696b..1befc471c5 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -291,11 +291,6 @@ __weak int mrc_cache_stash_data(int type, uint32_t version, return -1; } -/* Display the memory configuration */ -__weak void report_memory_config(void) -{ -} - /* SOC initialization after RAM is enabled */ __weak void soc_after_ram_init(struct romstage_params *params) { diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index 957b4c2a5d..99b5ba197e 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -241,44 +241,3 @@ void report_platform_info(void) report_pch_info(); report_igd_info(); } - -/* - * Dump in the log memory controller configuration as read from the memory - * controller registers. - */ -void report_memory_config(void) -{ - u32 addr_decoder_common, addr_decode_ch[2]; - int i; - - addr_decoder_common = MCHBAR32(0x5000); - addr_decode_ch[0] = MCHBAR32(0x5004); - addr_decode_ch[1] = MCHBAR32(0x5008); - - printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); - printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", - addr_decoder_common & 3, - (addr_decoder_common >> 2) & 3, - (addr_decoder_common >> 4) & 3); - - for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { - u32 ch_conf = addr_decode_ch[i]; - printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", - i, ch_conf); - printk(BIOS_DEBUG, " enhanced interleave mode %s\n", - ((ch_conf >> 22) & 1) ? "on" : "off"); - printk(BIOS_DEBUG, " rank interleave %s\n", - ((ch_conf >> 21) & 1) ? "on" : "off"); - printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", - ((ch_conf >> 0) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", - ((ch_conf >> 17) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? "" : ", selected"); - printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", - ((ch_conf >> 8) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", - ((ch_conf >> 18) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? ", selected" : ""); - } -} diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h index 6b6af36504..62544de186 100644 --- a/src/soc/intel/skylake/include/soc/bootblock.h +++ b/src/soc/intel/skylake/include/soc/bootblock.h @@ -13,6 +13,5 @@ void bootblock_pch_early_init(void); void bootblock_pch_init(void); void pch_early_iorange_init(void); void report_platform_info(void); -void report_memory_config(void); #endif