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drivers/intel/fsp1_1: Drop unused weak definitions 

The only FSP 1.1 platform is Braswell. Drop unused weak definitions for
functions where a non-weak definition always exists.

Tested with BUILD_TIMELESS=1, Facebook fbg1701 remains identical.

Change-Id: Ifaf40a1cd661b123911fbeaafeb2b7002559a435
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Angel Pons 2021-05-26 15:05:12 +02:00 committed by Felix Held
parent 54fc8b35d1
commit eca0d70c98
3 changed files with 0 additions and 50 deletions
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24
src/drivers/intel/fsp1_1/raminit.c
View File

@ -249,30 +249,6 @@ void raminit(struct romstage_params *params)
}
}
/* Initialize the UPD parameters for MemoryInit */
__weak void mainboard_memory_init_params(
struct romstage_params *params,
MEMORY_INIT_UPD *upd_ptr)
{
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
}
/* Display the UPD parameters for MemoryInit */
__weak void soc_display_memory_init_params(
const MEMORY_INIT_UPD *old, MEMORY_INIT_UPD *new)
{
printk(BIOS_SPEW, "UPD values for MemoryInit:\n");
hexdump32(BIOS_SPEW, new, sizeof(*new));
}
/* Initialize the UPD parameters for MemoryInit */
__weak void soc_memory_init_params(
struct romstage_params *params,
MEMORY_INIT_UPD *upd)
{
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
}
/* Initialize the SoC after MemoryInit */
__weak void mainboard_after_memory_init(void)
{

8
src/drivers/intel/fsp1_1/ramstage.c
View File

@ -171,14 +171,6 @@ void intel_silicon_init(void)
__weak void mainboard_silicon_init_params(
SILICON_INIT_UPD *params)
{
};
/* Display the UPD parameters for SiliconInit */
__weak void soc_display_silicon_init_params(
const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new)
{
printk(BIOS_SPEW, "UPD values for SiliconInit:\n");
hexdump32(BIOS_SPEW, new, sizeof(*new));
}
/* Initialize the UPD parameters for SiliconInit */

18
src/drivers/intel/fsp1_1/romstage.c
View File

@ -136,12 +136,6 @@ void cache_as_ram_stage_main(FSP_INFO_HEADER *fih)
post_code(0x38);
}
/* Initialize the power state */
__weak struct chipset_power_state *fill_power_state(void)
{
return NULL;
}
/* Board initialization before and after RAM is enabled */
__weak void mainboard_pre_raminit(struct romstage_params *params)
{
@ -284,18 +278,6 @@ __weak void mainboard_add_dimm_info(
{
}
/* Save the memory configuration data */
__weak int mrc_cache_stash_data(int type, uint32_t version,
const void *data, size_t size)
{
return -1;
}
/* SOC initialization after RAM is enabled */
__weak void soc_after_ram_init(struct romstage_params *params)
{
}
/* SOC initialization before RAM is enabled */
__weak void soc_pre_ram_init(struct romstage_params *params)
{