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armv7: added paranoia for cache library 

This adds some paranoia to cache manipulation routines:
- "memory" is added to the clobber list for functions which clean
  and/or invalidate dcache or TLB entries.
- Remove unneeded clobber list for read_sctlr()

Change-Id: Iaa82ef78bfdad4119f097c3b6db8219f29f832bc
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2928
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
David Hendricks 2013-03-26 21:26:51 -07:00 committed by Ronald G. Minnich
parent dbc11e2f76
commit eca48438fc
1 changed files with 9 additions and 9 deletions
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18
src/arch/armv7/include/arch/cache.h
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@ -93,7 +93,7 @@ static inline void isb(void)
/* invalidate entire data TLB */
static inline void dtlbiall(void)
{
asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0));
asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0) : "memory");
}
/* invalidate entire instruction TLB */
@ -105,7 +105,7 @@ static inline void itlbiall(void)
/* invalidate entire unified TLB */
static inline void tlbiall(void)
{
asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0) : "memory");
}
/* write data access control register (DACR) */
@ -147,31 +147,31 @@ static inline void bpiall(void)
/* data cache clean and invalidate by MVA to PoC */
static inline void dccimvac(unsigned long mva)
{
asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva));
asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva) : "memory");
}
/* data cache invalidate by set/way */
static inline void dccisw(uint32_t val)
{
asm volatile ("mcr p15, 0, %0, c7, c14, 2" : : "r" (val));
asm volatile ("mcr p15, 0, %0, c7, c14, 2" : : "r" (val) : "memory");
}
/* data cache clean by MVA to PoC */
static inline void dccmvac(unsigned long mva)
{
asm volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" (mva));
asm volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" (mva) : "memory");
}
/* data cache invalidate by MVA to PoC */
static inline void dcimvac(unsigned long mva)
{
asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva));
asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva) : "memory");
}
/* data cache invalidate by set/way */
static inline void dcisw(uint32_t val)
{
asm volatile ("mcr p15, 0, %0, c7, c6, 2" : : "r" (val));
asm volatile ("mcr p15, 0, %0, c7, c6, 2" : : "r" (val) : "memory");
}
/* instruction cache invalidate all by PoU */
@ -223,12 +223,12 @@ static inline void write_csselr(uint32_t val)
static inline unsigned int read_sctlr(void)
{
unsigned int val;
asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val) : : "cc");
asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val));
return val;
}
/* write system control register (SCTLR) */
static inline void write_sctlr(unsigned int val)
static inline void write_sctlr(uint32_t val)
{
asm volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val) : "cc");
isb();