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mainboard/asus/kgpe-d16: Enable romstage spinlocks 

Change-Id: Iac1adbeacdcded7faff2443b78a491cbb8a90fe8
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12628
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Timothy Pearson 2015-11-05 13:16:55 -06:00 committed by Martin Roth
parent 44d5342835
commit ecd4cfcb86
2 changed files with 16 additions and 5 deletions
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1
src/mainboard/asus/kgpe-d16/Kconfig
View File

@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOUTHBRIDGE_AMD_SUBTYPE_SP5100 select SOUTHBRIDGE_AMD_SUBTYPE_SP5100
select SUPERIO_NUVOTON_NCT5572D select SUPERIO_NUVOTON_NCT5572D
select PARALLEL_CPU_INIT select PARALLEL_CPU_INIT
select HAVE_ROMSTAGE_CONSOLE_SPINLOCK
select HAVE_HARD_RESET select HAVE_HARD_RESET
select HAVE_OPTION_TABLE select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT select HAVE_CMOS_DEFAULT

20
src/mainboard/asus/kgpe-d16/romstage.c
View File

@ -312,6 +312,18 @@ static void execute_memory_test(void)
} }
#endif #endif
static spinlock_t printk_spinlock CAR_GLOBAL;
spinlock_t* romstage_console_lock(void)
{
return car_get_var_ptr(&printk_spinlock);
}
void initialize_romstage_console_lock(void)
{
car_get_var(printk_spinlock) = SPIN_LOCK_UNLOCKED;
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
uint32_t esp; uint32_t esp;
@ -338,6 +350,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
timestamp_init(timestamp_get()); timestamp_init(timestamp_get());
timestamp_add_now(TS_START_ROMSTAGE); timestamp_add_now(TS_START_ROMSTAGE);
/* Initialize the printk spinlock */
initialize_romstage_console_lock();
/* Nothing special needs to be done to find bus 0 */ /* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */ /* Allow the HT devices to be found */
set_bsp_node_CHtExtNodeCfgEn(); set_bsp_node_CHtExtNodeCfgEn();
@ -407,11 +422,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x36); post_code(0x36);
/* Wait for all the APs core0 started by finalize_node_setup. */ /* Wait for all the APs core0 started by finalize_node_setup. */
/* FIXME: A bunch of cores are going to start output to serial at once.
* It would be nice to fix up prink spinlocks for ROM XIP mode.
* I think it could be done by putting the spinlock flag in the cache
* of the BSP located right after sysinfo.
*/
wait_all_core0_started(); wait_all_core0_started();
/* run _early_setup before soft-reset. */ /* run _early_setup before soft-reset. */