mainboard/asus/kgpe-d16: Enable romstage spinlocks
Change-Id: Iac1adbeacdcded7faff2443b78a491cbb8a90fe8 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12628 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select SOUTHBRIDGE_AMD_SUBTYPE_SP5100
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select SUPERIO_NUVOTON_NCT5572D
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select PARALLEL_CPU_INIT
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select HAVE_ROMSTAGE_CONSOLE_SPINLOCK
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select HAVE_HARD_RESET
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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@ -312,6 +312,18 @@ static void execute_memory_test(void)
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}
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#endif
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static spinlock_t printk_spinlock CAR_GLOBAL;
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spinlock_t* romstage_console_lock(void)
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{
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return car_get_var_ptr(&printk_spinlock);
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}
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void initialize_romstage_console_lock(void)
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{
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car_get_var(printk_spinlock) = SPIN_LOCK_UNLOCKED;
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}
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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uint32_t esp;
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@ -338,6 +350,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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timestamp_init(timestamp_get());
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timestamp_add_now(TS_START_ROMSTAGE);
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/* Initialize the printk spinlock */
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initialize_romstage_console_lock();
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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set_bsp_node_CHtExtNodeCfgEn();
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@ -407,11 +422,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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post_code(0x36);
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/* Wait for all the APs core0 started by finalize_node_setup. */
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/* FIXME: A bunch of cores are going to start output to serial at once.
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* It would be nice to fix up prink spinlocks for ROM XIP mode.
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* I think it could be done by putting the spinlock flag in the cache
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* of the BSP located right after sysinfo.
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*/
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wait_all_core0_started();
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/* run _early_setup before soft-reset. */
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