rockchip/rk3399: mipi: Fix LOOP_DIV_HIGH_SEL to be 4 bits wide
Accroding to datasheet, feedback divider register high value is only 4 bit, it currently uses 5 bit, so correct it. Change-Id: I1fe9fc076b712f27407c5f2735b15e64fb55e72e Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
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@ -197,7 +197,7 @@ check_member(rk_mipi_regs, dsi_int_msk1, 0xc8);
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#define LOW_PROGRAM_EN 0
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#define HIGH_PROGRAM_EN BIT(7)
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#define LOOP_DIV_LOW_SEL(val) ((val - 1) & 0x1f)
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#define LOOP_DIV_HIGH_SEL(val) (((val - 1) >> 5) & 0x1f)
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#define LOOP_DIV_HIGH_SEL(val) (((val - 1) >> 5) & 0xf)
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#define PLL_LOOP_DIV_EN BIT(5)
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#define PLL_INPUT_DIV_EN BIT(4)
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