rockchip/rk3399: mipi: Fix LOOP_DIV_HIGH_SEL to be 4 bits wide

Accroding to datasheet, feedback divider register high value is only
4 bit, it currently uses 5 bit, so correct it.

Change-Id: I1fe9fc076b712f27407c5f2735b15e64fb55e72e
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Lin Huang 2017-11-16 09:52:27 +08:00 committed by Julius Werner
parent 5220e5fba6
commit ecd600a0ca
1 changed files with 1 additions and 1 deletions

View File

@ -197,7 +197,7 @@ check_member(rk_mipi_regs, dsi_int_msk1, 0xc8);
#define LOW_PROGRAM_EN 0
#define HIGH_PROGRAM_EN BIT(7)
#define LOOP_DIV_LOW_SEL(val) ((val - 1) & 0x1f)
#define LOOP_DIV_HIGH_SEL(val) (((val - 1) >> 5) & 0x1f)
#define LOOP_DIV_HIGH_SEL(val) (((val - 1) >> 5) & 0xf)
#define PLL_LOOP_DIV_EN BIT(5)
#define PLL_INPUT_DIV_EN BIT(4)