GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

sb/intel/bd82x6x,ibexpeak: Move UPRWC definition 

Locate it with all the other PM IO registers.

Change-Id: I779b2e313c9d8370c66c4adb4f6f4d4cf5b4e7dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2023-05-05 09:27:42 +03:00 committed by Lean Sheng Tan
parent ab368d96d7
commit ece06dc2d1
2 changed files with 10 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/southbridge/intel/bd82x6x/pch.h
View File

@ -64,10 +64,6 @@ extern const struct southbridge_usb_port mainboard_usb_ports[14];
void early_usb_init(const struct southbridge_usb_port *portmap);
/* PM I/O Space */
#define UPRWC 0x3c
#define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */
/* PCI Configuration Space (D30:F0): PCI2PCI */
#define PSTS 0x06
#define SMLT 0x1b
@ -459,6 +455,11 @@ void early_usb_init(const struct southbridge_usb_port *portmap);
#define SMI_STS 0x34
#define ALT_GP_SMI_EN 0x38
#define ALT_GP_SMI_STS 0x3a
/* PM I/O Space */
#define UPRWC 0x3c
#define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */
#define GPE_CNTL 0x42
#define DEVACT_STS 0x44
#define PM2_CNT 0x50 // mobile only

9
src/southbridge/intel/ibexpeak/pch.h
View File

@ -66,10 +66,6 @@ void pch_enable(struct device *dev);
#define MAINBOARD_POWER_ON 1
#define MAINBOARD_POWER_KEEP 2
/* PM I/O Space */
#define UPRWC 0x3c
#define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */
/* PCI Configuration Space (D30:F0): PCI2PCI */
#define PSTS 0x06
#define SMLT 0x1b
@ -440,6 +436,11 @@ void pch_enable(struct device *dev);
#define SMI_STS 0x34
#define ALT_GP_SMI_EN 0x38
#define ALT_GP_SMI_STS 0x3a
/* PM I/O Space */
#define UPRWC 0x3c
#define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */
#define GPE_CNTL 0x42
#define DEVACT_STS 0x44
#define PM2_CNT 0x50 // mobile only