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soc/intel/elkhartlake: Update Kconfig 

Update Kconfig:
1. use FSP2.1 instead of 2.2
2. remove HECI_DISABLE_USING_SMM config
3. update CAR related stack & ram size
4. update FSP heap size
5. set IED region size = 0 as it is not used
6. update SMM TSEG size
7. update RP & I2C max device #s
8. update UART base address

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I6a44d357d71be706f402a6b2a4f2d4e7c0eeb4a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45078
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tan, Lean Sheng 2020-09-03 07:32:48 -07:00 committed by Patrick Georgi
parent 270a32370d
commit ece0fe3f23
1 changed files with 15 additions and 13 deletions
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28
src/soc/intel/elkhartlake/Kconfig
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@ -30,7 +30,7 @@ config CPU_SPECIFIC_OPTIONS
select PARALLEL_MP select PARALLEL_MP
select PARALLEL_MP_AP_WORK select PARALLEL_MP_AP_WORK
select MICROCODE_BLOB_UNDISCLOSED select MICROCODE_BLOB_UNDISCLOSED
select PLATFORM_USES_FSP2_2 select PLATFORM_USES_FSP2_1
select FSP_PEIM_TO_PEIM_INTERFACE select FSP_PEIM_TO_PEIM_INTERFACE
select REG_SCRIPT select REG_SCRIPT
select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_GLOBAL_RESET_ENABLE_LOCK
@ -61,29 +61,31 @@ config CPU_SPECIFIC_OPTIONS
select UDELAY_TSC select UDELAY_TSC
select UDK_202005_BINDING select UDK_202005_BINDING
select DISPLAY_FSP_VERSION_INFO select DISPLAY_FSP_VERSION_INFO
select HECI_DISABLE_USING_SMM
config MAX_CPUS
int
default 4
config DCACHE_RAM_BASE config DCACHE_RAM_BASE
default 0xfef00000 default 0xfef00000
config DCACHE_RAM_SIZE config DCACHE_RAM_SIZE
default 0x80000 default 0xc0000
help help
The size of the cache-as-ram region required during bootblock The size of the cache-as-ram region required during bootblock
and/or romstage. and/or romstage.
config DCACHE_BSP_STACK_SIZE config DCACHE_BSP_STACK_SIZE
hex hex
default 0x30400 default 0x30000
help help
The amount of anticipated stack usage in CAR by bootblock and The amount of anticipated stack usage in CAR by bootblock and
other stages. In the case of FSP_USES_CB_STACK default value other stages. In the case of FSP_USES_CB_STACK default value will be
will be sum of FSP-M stack requirement(192 KiB) and CB romstage sum of FSP-M stack requirement (192KiB) and CB romstage stack requirement (~1KiB).
stack requirement(~1KiB).
config FSP_TEMP_RAM_SIZE config FSP_TEMP_RAM_SIZE
hex hex
default 0x20000 default 0x40000
help help
The amount of anticipated heap usage in CAR by FSP. The amount of anticipated heap usage in CAR by FSP.
Refer to Platform FSP integration guide document to know Refer to Platform FSP integration guide document to know
@ -95,7 +97,7 @@ config IFD_CHIPSET
config IED_REGION_SIZE config IED_REGION_SIZE
hex hex
default 0x400000 default 0x0
config HEAP_SIZE config HEAP_SIZE
hex hex
@ -103,7 +105,7 @@ config HEAP_SIZE
config MAX_ROOT_PORTS config MAX_ROOT_PORTS
int int
default 8 default 7
config MAX_PCIE_CLOCKS config MAX_PCIE_CLOCKS
int int
@ -111,7 +113,7 @@ config MAX_PCIE_CLOCKS
config SMM_TSEG_SIZE config SMM_TSEG_SIZE
hex hex
default 0x800000 default 0x1000000
config SMM_RESERVED_SIZE config SMM_RESERVED_SIZE
hex hex
@ -148,7 +150,7 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
config SOC_INTEL_I2C_DEV_MAX config SOC_INTEL_I2C_DEV_MAX
int int
default 6 default 8
config SOC_INTEL_UART_DEV_MAX config SOC_INTEL_UART_DEV_MAX
int int
@ -156,7 +158,7 @@ config SOC_INTEL_UART_DEV_MAX
config CONSOLE_UART_BASE_ADDRESS config CONSOLE_UART_BASE_ADDRESS
hex hex
default 0xfe032000 default 0xfe042000
depends on INTEL_LPSS_UART_FOR_CONSOLE depends on INTEL_LPSS_UART_FOR_CONSOLE
# Clock divider parameters for 115200 baud rate # Clock divider parameters for 115200 baud rate