diff --git a/src/cpu/intel/fsp_model_206ax/finalize.c b/src/cpu/intel/fsp_model_206ax/finalize.c
index 53a6cc9c15..2d5973b984 100644
--- a/src/cpu/intel/fsp_model_206ax/finalize.c
+++ b/src/cpu/intel/fsp_model_206ax/finalize.c
@@ -69,7 +69,7 @@ void intel_model_206ax_finalize_smm(void)
 	msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
 #endif
 
-	/* Lock TM interupts - route thermal events to all processors */
+	/* Lock TM interrupts - route thermal events to all processors */
 	msr_set_bit(MSR_MISC_PWR_MGMT, 22);
 
 	/* Lock memory configuration to protect SMM */
diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c
index ba2538702e..ce22e629e8 100644
--- a/src/cpu/intel/haswell/finalize.c
+++ b/src/cpu/intel/haswell/finalize.c
@@ -72,7 +72,7 @@ void intel_cpu_haswell_finalize_smm(void)
 	msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
 #endif
 
-	/* Lock TM interupts - route thermal events to all processors */
+	/* Lock TM interrupts - route thermal events to all processors */
 	msr_set_bit(MSR_MISC_PWR_MGMT, 22);
 
 	/* Lock memory configuration to protect SMM */
diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c
index 5e7b3d847c..8425f6afe6 100644
--- a/src/cpu/intel/model_2065x/finalize.c
+++ b/src/cpu/intel/model_2065x/finalize.c
@@ -52,6 +52,6 @@ void intel_model_2065x_finalize_smm(void)
 	if (cpuid_ecx(1) & (1 << 25))
 		msr_set_bit(MSR_FEATURE_CONFIG, 0);
 
-	/* Lock TM interupts - route thermal events to all processors */
+	/* Lock TM interrupts - route thermal events to all processors */
 	msr_set_bit(MSR_MISC_PWR_MGMT, 22);
 }
diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c
index 50f49772d4..7d3cc2ee0e 100644
--- a/src/cpu/intel/model_206ax/finalize.c
+++ b/src/cpu/intel/model_206ax/finalize.c
@@ -70,7 +70,7 @@ void intel_model_206ax_finalize_smm(void)
 	msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
 #endif
 
-	/* Lock TM interupts - route thermal events to all processors */
+	/* Lock TM interrupts - route thermal events to all processors */
 	msr_set_bit(MSR_MISC_PWR_MGMT, 22);
 
 	/* Lock memory configuration to protect SMM */
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
index a87ce754fa..5a9739c9b9 100644
--- a/src/cpu/x86/16bit/entry16.inc
+++ b/src/cpu/x86/16bit/entry16.inc
@@ -89,7 +89,7 @@ _start16bit:
 	 * must be loaded at or above 0xffff0000 or below 0x100000.
 	 *
 	 * The linker scripts computes gdtptr16_offset by simply returning
-	 * the low 16 bits.  This means that the intial segment used
+	 * the low 16 bits.  This means that the initial segment used
 	 * when start is called must be 64K aligned.  This should not
 	 * restrict the address as the ip address can be anything.
 	 *
diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S
index 83606bd920..ba5ae3e1ae 100644
--- a/src/cpu/x86/sipi_vector.S
+++ b/src/cpu/x86/sipi_vector.S
@@ -17,7 +17,7 @@
 #include <cpu/x86/cr.h>
 #include <cpu/amd/mtrr.h>
 
-/* The SIPI vector is responsible for initializing the APs in the sytem. It
+/* The SIPI vector is responsible for initializing the APs in the system. It
  * loads microcode, sets up MSRs, and enables caching before calling into
  * C code. */