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nb/intel/x4x: Change signature of `decode_pciebar` 

Rename it and make it return an int, like other northbridges do.

Change-Id: I8bbf28350976547c83e039731d316e0911197d54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2020-08-03 15:44:27 +02:00
parent f4fa1e1d06
commit ecec9474d8
4 changed files with 4 additions and 4 deletions
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2
src/northbridge/intel/x4x/acpi.c
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@ -12,7 +12,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
u32 pciexbar = 0; u32 pciexbar = 0;
u32 length = 0; u32 length = 0;
if (!decode_pciebar(&pciexbar, &length)) if (!decode_pcie_bar(&pciexbar, &length))
return current; return current;
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,

2
src/northbridge/intel/x4x/memmap.c
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@ -57,7 +57,7 @@ u32 decode_tseg_size(const u32 esmramc)
} }
} }
u8 decode_pciebar(u32 *const base, u32 *const len) int decode_pcie_bar(u32 *const base, u32 *const len)
{ {
*base = 0; *base = 0;
*len = 0; *len = 0;

2
src/northbridge/intel/x4x/northbridge.c
View File

@ -111,7 +111,7 @@ static void mch_domain_read_resources(struct device *dev)
top32memk - (DEFAULT_HECIBAR >> 10), top32memk - (DEFAULT_HECIBAR >> 10),
IORESOURCE_RESERVE); IORESOURCE_RESERVE);
if (decode_pciebar(&pcie_config_base, &pcie_config_size)) { if (decode_pcie_bar(&pcie_config_base, &pcie_config_size)) {
printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
"size=0x%x\n", pcie_config_base, pcie_config_size); "size=0x%x\n", pcie_config_base, pcie_config_size);
fixed_mem_resource(dev, index++, pcie_config_base >> 10, fixed_mem_resource(dev, index++, pcie_config_base >> 10,

2
src/northbridge/intel/x4x/x4x.h
View File

@ -331,7 +331,7 @@ void mb_pre_raminit_setup(int s3_resume);
u32 decode_igd_memory_size(u32 gms); u32 decode_igd_memory_size(u32 gms);
u32 decode_igd_gtt_size(u32 gsm); u32 decode_igd_gtt_size(u32 gsm);
u32 decode_tseg_size(const u32 esmramc); u32 decode_tseg_size(const u32 esmramc);
u8 decode_pciebar(u32 *const base, u32 *const len); int decode_pcie_bar(u32 *const base, u32 *const len);
void sdram_initialize(int boot_path, const u8 *spd_map); void sdram_initialize(int boot_path, const u8 *spd_map);
void do_raminit(struct sysinfo *, int fast_boot); void do_raminit(struct sysinfo *, int fast_boot);
void rcven(struct sysinfo *s); void rcven(struct sysinfo *s);