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sandybridge ivybridge: Treat native init as first class citizen 

This is a sad story. We have three different code paths for
sandybridge and ivybridge: proper native path, google MRC path, and,
everyone's favorite: Intel FSP path. For the purpose of this patch,
the FSP path lives in its own little world, and doesn't concern us.

Since MRC was first, when native files and variables were added, they
were suffixed with "_native" to separate them from the existing code.
This can cause confusion, as the suffix might make the native files
seem parasitical.

This has been bothering me for many months. MRC should be the
parasitical path, especially since we fully support native init, and
it works more reliably, on a wider range of hardware. There have been
a few board ports that never made it to coreboot.org because MRC would
hang.

gigabyte/ga-b75m-d3h is a prime example: it did not work with MRC, so
the effort was abandoned at first. Once the native path became
available, the effort was restarted and the board is now supported.

In honor of the hackers and pioneers who made the native code
possible, rename things so that their effort is the first class
citizen.

Change-Id: Ic86cee5e00bf7f598716d3d15d1ea81ca673932f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11788
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
This commit is contained in:
Alexandru Gagniuc 2015-09-28 21:39:12 -07:00
parent ac1f4b86f4
commit ecf2eb463f
37 changed files with 4933 additions and 4933 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/Kconfig
View File

@ -246,8 +246,8 @@ config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
config FLASHMAP_OFFSET
hex "Flash Map Offset"
default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE
default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE
default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC
default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE_MRC
default CBFS_SIZE if !ARCH_X86
default 0
help
@ -337,9 +337,9 @@ source "src/mainboard/Kconfig"
config CBFS_SIZE
hex "Size of CBFS filesystem in ROM"
default 0x100000 if HAVE_INTEL_FIRMWARE || \
NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_SANDYBRIDGE || \
NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || \
NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE || \
NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC || \
NORTHBRIDGE_INTEL_IVYBRIDGE_MRC || NORTHBRIDGE_INTEL_IVYBRIDGE || \
NORTHBRIDGE_INTEL_SANDYBRIDGE || \
NORTHBRIDGE_INTEL_NEHALEM || SOC_INTEL_BRASWELL || \
SOC_INTEL_BROADWELL
default 0x200000 if SOC_INTEL_SKYLAKE

4
src/cpu/intel/Makefile.inc
View File

@ -17,10 +17,10 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370
subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA988B) += socket_rPGA988B
subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA989) += socket_rPGA989
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC) += model_206ax
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += model_206ax
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_MRC) += model_206ax
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += model_206ax
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += model_206ax
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE) += fsp_model_206ax
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE) += fsp_model_206ax

2
src/mainboard/gigabyte/ga-b75m-d3h/Kconfig
View File

@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS
def_bool y
select ARCH_X86
select CPU_INTEL_SOCKET_LGA1155
select NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
select NORTHBRIDGE_INTEL_IVYBRIDGE
select SOUTHBRIDGE_INTEL_C216
select SUPERIO_ITE_IT8728F
select BOARD_ROMSIZE_KB_8192

2
src/mainboard/gigabyte/ga-b75m-d3v/Kconfig
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@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS
def_bool y
select ARCH_X86
select CPU_INTEL_SOCKET_LGA1155
select NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
select NORTHBRIDGE_INTEL_SANDYBRIDGE
select SOUTHBRIDGE_INTEL_C216
select CPU_MICROCODE_CBFS_NONE
select SUPERIO_ITE_IT8728F

2
src/mainboard/google/butterfly/Kconfig
View File

@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SYSTEM_TYPE_LAPTOP
select CPU_INTEL_SOCKET_RPGA989
select NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
select NORTHBRIDGE_INTEL_IVYBRIDGE
select SOUTHBRIDGE_INTEL_C216
select EC_QUANTA_ENE_KB3940Q
select BOARD_ROMSIZE_KB_8192

2
src/mainboard/google/link/Kconfig
View File

@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SYSTEM_TYPE_LAPTOP
select CPU_INTEL_SOCKET_RPGA989
select NORTHBRIDGE_INTEL_IVYBRIDGE
select NORTHBRIDGE_INTEL_IVYBRIDGE_MRC
select SOUTHBRIDGE_INTEL_C216
select BOARD_ROMSIZE_KB_8192
select EC_GOOGLE_CHROMEEC

2
src/mainboard/google/parrot/Kconfig
View File

@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SYSTEM_TYPE_LAPTOP
select CPU_INTEL_SOCKET_RPGA989
select NORTHBRIDGE_INTEL_IVYBRIDGE
select NORTHBRIDGE_INTEL_IVYBRIDGE_MRC
select SOUTHBRIDGE_INTEL_C216
select EC_COMPAL_ENE932
select BOARD_ROMSIZE_KB_8192

2
src/mainboard/google/stout/Kconfig
View File

@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SYSTEM_TYPE_LAPTOP
select CPU_INTEL_SOCKET_RPGA989
select NORTHBRIDGE_INTEL_IVYBRIDGE
select NORTHBRIDGE_INTEL_IVYBRIDGE_MRC
select SOUTHBRIDGE_INTEL_C216
select EC_QUANTA_IT8518
select BOARD_ROMSIZE_KB_8192

2
src/mainboard/intel/emeraldlake2/Kconfig
View File

@ -3,7 +3,7 @@ if BOARD_INTEL_EMERALDLAKE2
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_INTEL_SOCKET_RPGA989
select NORTHBRIDGE_INTEL_IVYBRIDGE
select NORTHBRIDGE_INTEL_IVYBRIDGE_MRC
select SOUTHBRIDGE_INTEL_C216
select SUPERIO_SMSC_SIO1007
select BOARD_ROMSIZE_KB_8192

2
src/mainboard/kontron/ktqm77/Kconfig
View File

@ -3,7 +3,7 @@ if BOARD_KONTRON_KTQM77
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_INTEL_SOCKET_RPGA989
select NORTHBRIDGE_INTEL_IVYBRIDGE
select NORTHBRIDGE_INTEL_IVYBRIDGE_MRC
select SOUTHBRIDGE_INTEL_C216
select SUPERIO_WINBOND_W83627DHG
select EC_KONTRON_IT8516E

2
src/mainboard/lenovo/t420s/Kconfig
View File

@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SYSTEM_TYPE_LAPTOP
select CPU_INTEL_SOCKET_RPGA988B
select NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
select NORTHBRIDGE_INTEL_SANDYBRIDGE
select SOUTHBRIDGE_INTEL_BD82X6X
select EC_LENOVO_PMH7
select EC_LENOVO_H8

2
src/mainboard/lenovo/t430s/Kconfig
View File

@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SYSTEM_TYPE_LAPTOP
select CPU_INTEL_SOCKET_RPGA989
select NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
select NORTHBRIDGE_INTEL_IVYBRIDGE
select SOUTHBRIDGE_INTEL_C216
select EC_LENOVO_PMH7
select EC_LENOVO_H8

2
src/mainboard/lenovo/t520/Kconfig
View File

@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SYSTEM_TYPE_LAPTOP
select CPU_INTEL_SOCKET_RPGA988B
select NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
select NORTHBRIDGE_INTEL_SANDYBRIDGE
select SOUTHBRIDGE_INTEL_BD82X6X
select EC_LENOVO_PMH7
select EC_LENOVO_H8

2
src/mainboard/lenovo/t530/Kconfig
View File

@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SYSTEM_TYPE_LAPTOP
select CPU_INTEL_SOCKET_RPGA989
select NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
select NORTHBRIDGE_INTEL_IVYBRIDGE
select SOUTHBRIDGE_INTEL_C216
select EC_LENOVO_PMH7
select EC_LENOVO_H8

2
src/mainboard/lenovo/x220/Kconfig
View File

@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SYSTEM_TYPE_LAPTOP
select CPU_INTEL_SOCKET_RPGA989
select NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
select NORTHBRIDGE_INTEL_SANDYBRIDGE
select SOUTHBRIDGE_INTEL_C216
select EC_LENOVO_PMH7
select EC_LENOVO_H8

2
src/mainboard/lenovo/x230/Kconfig
View File

@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SYSTEM_TYPE_LAPTOP
select CPU_INTEL_SOCKET_RPGA989
select NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
select NORTHBRIDGE_INTEL_IVYBRIDGE
select SOUTHBRIDGE_INTEL_C216
select EC_LENOVO_PMH7
select EC_LENOVO_H8

2
src/mainboard/samsung/lumpy/Kconfig
View File

@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select NORTHBRIDGE_INTEL_SANDYBRIDGE
select NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC
select SOUTHBRIDGE_INTEL_BD82X6X
select SUPERIO_SMSC_MEC1308
# LPC47N207 selected for external LPC card

2
src/mainboard/samsung/stumpy/Kconfig
View File

@ -9,7 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select NORTHBRIDGE_INTEL_SANDYBRIDGE
select NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC
select SOUTHBRIDGE_INTEL_BD82X6X
select SUPERIO_ITE_IT8772F
# LPC47N207 selected for external LPC card

30
src/northbridge/intel/sandybridge/Kconfig
View File

@ -17,14 +17,14 @@
## Foundation, Inc.
##
config NORTHBRIDGE_INTEL_SANDYBRIDGE
config NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC
bool
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
select CPU_INTEL_MODEL_206AX
select INTEL_GMA_ACPI
config NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
config NORTHBRIDGE_INTEL_SANDYBRIDGE
bool
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
@ -32,14 +32,14 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
select HAVE_DEBUG_RAM_SETUP
select INTEL_GMA_ACPI
config NORTHBRIDGE_INTEL_IVYBRIDGE_MRC
bool
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
select CPU_INTEL_MODEL_306AX
select INTEL_GMA_ACPI
config NORTHBRIDGE_INTEL_IVYBRIDGE
bool
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
select CPU_INTEL_MODEL_306AX
select INTEL_GMA_ACPI
config NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
bool
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
@ -47,7 +47,7 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
select HAVE_DEBUG_RAM_SETUP
select INTEL_GMA_ACPI
if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
if NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC || NORTHBRIDGE_INTEL_IVYBRIDGE_MRC || NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_SANDYBRIDGE
config VGA_BIOS_ID
string
@ -72,10 +72,10 @@ config MRC_CACHE_SIZE
config DCACHE_RAM_BASE
hex
default 0xff7e0000 if NORTHBRIDGE_INTEL_IVYBRIDGE
default 0xff7e0000 if NORTHBRIDGE_INTEL_SANDYBRIDGE
default 0xfefe0000 if NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
default 0xfefe0000 if NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
default 0xff7e0000 if NORTHBRIDGE_INTEL_IVYBRIDGE_MRC
default 0xff7e0000 if NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC
default 0xfefe0000 if NORTHBRIDGE_INTEL_IVYBRIDGE
default 0xfefe0000 if NORTHBRIDGE_INTEL_SANDYBRIDGE
config DCACHE_RAM_SIZE
hex
@ -91,7 +91,7 @@ config DCACHE_RAM_MRC_VAR_SIZE
config HAVE_MRC
bool "Add a System Agent binary"
depends on !NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE && !NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
depends on !NORTHBRIDGE_INTEL_IVYBRIDGE && !NORTHBRIDGE_INTEL_SANDYBRIDGE
help
Select this option to add a System Agent binary to
the resulting coreboot image.

14
src/northbridge/intel/sandybridge/Makefile.inc
View File

@ -17,7 +17,7 @@
# Foundation, Inc.
#
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE)$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE)$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE),y)
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC)$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_MRC),y)
ramstage-y += ram_calc.c
ramstage-y += northbridge.c
@ -29,14 +29,14 @@ ramstage-y += acpi.c
ramstage-y += mrccache.c
romstage-y += ram_calc.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_MRC) += raminit_mrc.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC) += raminit_mrc.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += raminit.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += romstage.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ../../../device/dram/ddr3.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += raminit.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += raminit_native.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += romstage_native.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += ../../../device/dram/ddr3.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += raminit_native.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += romstage_native.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += ../../../device/dram/ddr3.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += romstage.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ../../../device/dram/ddr3.c
romstage-y += mrccache.c
romstage-y += early_init.c
romstage-y += report_platform.c

3943
src/northbridge/intel/sandybridge/raminit.c
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File diff suppressed because it is too large Load Diff

293
src/northbridge/intel/sandybridge/raminit_mrc.c Normal file
View File

@ -0,0 +1,293 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#include <console/console.h>
#include <console/usb.h>
#include <bootmode.h>
#include <string.h>
#include <arch/io.h>
#include <cbmem.h>
#include <arch/cbfs.h>
#include <cbfs.h>
#include <ip_checksum.h>
#include <pc80/mc146818rtc.h>
#include <device/pci_def.h>
#include <halt.h>
#include "raminit.h"
#include "pei_data.h"
#include "sandybridge.h"
/* Management Engine is in the southbridge */
#include "southbridge/intel/bd82x6x/me.h"
/*
* MRC scrambler seed offsets should be reserved in
* mainboard cmos.layout and not covered by checksum.
*/
#if CONFIG_USE_OPTION_TABLE
#include "option_table.h"
#define CMOS_OFFSET_MRC_SEED (CMOS_VSTART_mrc_scrambler_seed >> 3)
#define CMOS_OFFSET_MRC_SEED_S3 (CMOS_VSTART_mrc_scrambler_seed_s3 >> 3)
#define CMOS_OFFSET_MRC_SEED_CHK (CMOS_VSTART_mrc_scrambler_seed_chk >> 3)
#else
#define CMOS_OFFSET_MRC_SEED 152
#define CMOS_OFFSET_MRC_SEED_S3 156
#define CMOS_OFFSET_MRC_SEED_CHK 160
#endif
void save_mrc_data(struct pei_data *pei_data)
{
u16 c1, c2, checksum;
struct mrc_data_container *mrcdata;
int output_len = ALIGN(pei_data->mrc_output_len, 16);
/* Save the MRC S3 restore data to cbmem */
mrcdata = cbmem_add
(CBMEM_ID_MRCDATA,
output_len + sizeof(struct mrc_data_container));
if (mrcdata != NULL) {
printk(BIOS_DEBUG, "Relocate MRC DATA from %p to %p (%u bytes)\n",
pei_data->mrc_output, mrcdata, output_len);
mrcdata->mrc_signature = MRC_DATA_SIGNATURE;
mrcdata->mrc_data_size = output_len;
mrcdata->reserved = 0;
memcpy(mrcdata->mrc_data, pei_data->mrc_output,
pei_data->mrc_output_len);
/* Zero the unused space in aligned buffer. */
if (output_len > pei_data->mrc_output_len)
memset(mrcdata->mrc_data+pei_data->mrc_output_len, 0,
output_len - pei_data->mrc_output_len);
mrcdata->mrc_checksum = compute_ip_checksum(mrcdata->mrc_data,
mrcdata->mrc_data_size);
}
/* Save the MRC seed values to CMOS */
cmos_write32(CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed);
printk(BIOS_DEBUG, "Save scrambler seed 0x%08x to CMOS 0x%02x\n",
pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
cmos_write32(CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3);
printk(BIOS_DEBUG, "Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n",
pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
/* Save a simple checksum of the seed values */
c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed,
sizeof(u32));
c2 = compute_ip_checksum((u8*)&pei_data->scrambler_seed_s3,
sizeof(u32));
checksum = add_ip_checksums(sizeof(u32), c1, c2);
cmos_write(checksum & 0xff, CMOS_OFFSET_MRC_SEED_CHK);
cmos_write((checksum >> 8) & 0xff, CMOS_OFFSET_MRC_SEED_CHK+1);
}
static void prepare_mrc_cache(struct pei_data *pei_data)
{
struct mrc_data_container *mrc_cache;
u16 c1, c2, checksum, seed_checksum;
// preset just in case there is an error
pei_data->mrc_input = NULL;
pei_data->mrc_input_len = 0;
/* Read scrambler seeds from CMOS */
pei_data->scrambler_seed = cmos_read32(CMOS_OFFSET_MRC_SEED);
printk(BIOS_DEBUG, "Read scrambler seed 0x%08x from CMOS 0x%02x\n",
pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
pei_data->scrambler_seed_s3 = cmos_read32(CMOS_OFFSET_MRC_SEED_S3);
printk(BIOS_DEBUG, "Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n",
pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
/* Compute seed checksum and compare */
c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed,
sizeof(u32));
c2 = compute_ip_checksum((u8*)&pei_data->scrambler_seed_s3,
sizeof(u32));
checksum = add_ip_checksums(sizeof(u32), c1, c2);
seed_checksum = cmos_read(CMOS_OFFSET_MRC_SEED_CHK);
seed_checksum |= cmos_read(CMOS_OFFSET_MRC_SEED_CHK+1) << 8;
if (checksum != seed_checksum) {
printk(BIOS_ERR, "%s: invalid seed checksum\n", __func__);
pei_data->scrambler_seed = 0;
pei_data->scrambler_seed_s3 = 0;
return;
}
if ((mrc_cache = find_current_mrc_cache()) == NULL) {
/* error message printed in find_current_mrc_cache */
return;
}
pei_data->mrc_input = mrc_cache->mrc_data;
pei_data->mrc_input_len = mrc_cache->mrc_data_size;
printk(BIOS_DEBUG, "%s: at %p, size %x checksum %04x\n",
__func__, pei_data->mrc_input,
pei_data->mrc_input_len, mrc_cache->mrc_checksum);
}
static const char* ecc_decoder[] = {
"inactive",
"active on IO",
"disabled on IO",
"active"
};
/*
* Dump in the log memory controller configuration as read from the memory
* controller registers.
*/
static void report_memory_config(void)
{
u32 addr_decoder_common, addr_decode_ch[2];
int i;
addr_decoder_common = MCHBAR32(0x5000);
addr_decode_ch[0] = MCHBAR32(0x5004);
addr_decode_ch[1] = MCHBAR32(0x5008);
printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
(MCHBAR32(0x5e04) * 13333 * 2 + 50)/100);
printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
addr_decoder_common & 3,
(addr_decoder_common >> 2) & 3,
(addr_decoder_common >> 4) & 3);
for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
u32 ch_conf = addr_decode_ch[i];
printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n",
i, ch_conf);
printk(BIOS_DEBUG, " ECC %s\n",
ecc_decoder[(ch_conf >> 24) & 3]);
printk(BIOS_DEBUG, " enhanced interleave mode %s\n",
((ch_conf >> 22) & 1) ? "on" : "off");
printk(BIOS_DEBUG, " rank interleave %s\n",
((ch_conf >> 21) & 1) ? "on" : "off");
printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n",
((ch_conf >> 0) & 0xff) * 256,
((ch_conf >> 19) & 1) ? 16 : 8,
((ch_conf >> 17) & 1) ? "dual" : "single",
((ch_conf >> 16) & 1) ? "" : ", selected");
printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n",
((ch_conf >> 8) & 0xff) * 256,
((ch_conf >> 20) & 1) ? 16 : 8,
((ch_conf >> 18) & 1) ? "dual" : "single",
((ch_conf >> 16) & 1) ? ", selected" : "");
}
}
static void post_system_agent_init(struct pei_data *pei_data)
{
/* If PCIe init is skipped, set the PEG clock gating */
if (!pei_data->pcie_init)
MCHBAR32(0x7010) = MCHBAR32(0x7010) | 0x01;
}
/**
* Find PEI executable in coreboot filesystem and execute it.
*
* @param pei_data: configuration data for UEFI PEI reference code
*/
void sdram_initialize(struct pei_data *pei_data)
{
struct sys_info sysinfo;
int (*entry) (struct pei_data *pei_data) __attribute__ ((regparm(1)));
report_platform_info();
/* Wait for ME to be ready */
intel_early_me_init();
intel_early_me_uma_size();
printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n");
memset(&sysinfo, 0, sizeof(sysinfo));
sysinfo.boot_path = pei_data->boot_mode;
/*
* Do not pass MRC data in for recovery mode boot,
* Always pass it in for S3 resume.
*/
if (!recovery_mode_enabled() || pei_data->boot_mode == 2)
prepare_mrc_cache(pei_data);
/* If MRC data is not found we cannot continue S3 resume. */
if (pei_data->boot_mode == 2 && !pei_data->mrc_input) {
printk(BIOS_DEBUG, "Giving up in sdram_initialize: No MRC data\n");
outb(0x6, 0xcf9);
halt();
}
/* Pass console handler in pei_data */
pei_data->tx_byte = do_putchar;
/* Locate and call UEFI System Agent binary. */
entry = cbfs_boot_map_with_leak("mrc.bin", CBFS_TYPE_MRC, NULL);
if (entry) {
int rv;
rv = entry (pei_data);
if (rv) {
switch (rv) {
case -1:
printk(BIOS_ERR, "PEI version mismatch.\n");
break;
case -2:
printk(BIOS_ERR, "Invalid memory frequency.\n");
break;
default:
printk(BIOS_ERR, "MRC returned %x.\n", rv);
}
die("Nonzero MRC return value.\n");
}
} else {
die("UEFI PEI System Agent not found.\n");
}
#if CONFIG_USBDEBUG_IN_ROMSTAGE
/* mrc.bin reconfigures USB, so reinit it to have debug */
usbdebug_init();
#endif
/* For reference print the System Agent version
* after executing the UEFI PEI stage.
*/
u32 version = MCHBAR32(0x5034);
printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n",
version >> 24 , (version >> 16) & 0xff,
(version >> 8) & 0xff, version & 0xff);
/* Send ME init done for SandyBridge here. This is done
* inside the SystemAgent binary on IvyBridge. */
if (BASE_REV_SNB ==
(pci_read_config16(PCI_CPU_DEVICE, PCI_DEVICE_ID) & BASE_REV_MASK))
intel_early_me_init_done(ME_INIT_STATUS_SUCCESS);
else
intel_early_me_status();
post_system_agent_init(pei_data);
report_memory_config();
}

3902
src/northbridge/intel/sandybridge/raminit_native.c
View File

File diff suppressed because it is too large Load Diff

0
src/northbridge/intel/sandybridge/romstage_native.c → src/northbridge/intel/sandybridge/romstage.c
View File

10
src/southbridge/intel/bd82x6x/Makefile.inc
View File

@ -47,13 +47,13 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c
romstage-y += early_smbus.c me_status.c gpio.c
romstage-y += reset.c
romstage-y += early_spi.c early_pch.c
romstage-y += early_spi.c early_pch_common.c
romstage-y += early_rcba.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += early_me.c early_usb.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += early_me.c early_usb.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c early_usb_native.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c early_usb_native.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_MRC) += early_me_mrc.c early_usb_mrc.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC) += early_me_mrc.c early_usb_mrc.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += early_thermal.c early_pch.c early_me.c early_usb.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += early_thermal.c early_pch.c early_me.c early_usb.c
ramstage-y += madt.c

129
src/southbridge/intel/bd82x6x/early_me.c
View File

@ -44,13 +44,6 @@ static inline void pci_read_dword_ptr(void *ptr, int offset)
memcpy(ptr, &dword, sizeof(dword));
}
static inline void pci_write_dword_ptr(void *ptr, int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
pci_write_config32(PCH_ME_DEV, offset, dword);
}
void intel_early_me_status(void)
{
struct me_hfs hfs;
@ -125,64 +118,136 @@ static inline void set_global_reset(int enable)
int intel_early_me_init_done(u8 status)
{
u8 reset;
int count;
u8 reset, errorcode, opmode;
u16 reg16;
u32 mebase_l, mebase_h;
struct me_hfs hfs;
u32 millisec;
u32 hfs, me_fws2;
struct me_did did = {
.init_done = ME_INIT_DONE,
.status = status
};
u32 meDID;
hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xff000) >> 12;
opmode = (hfs & 0xf0) >> 4;
errorcode = hfs & 0xf;
if (opmode != ME_HFS_MODE_NORMAL) {
printk(BIOS_NOTICE, "ME: Wrong mode : %d\n", opmode);
//return 0;
}
if (errorcode) {
printk(BIOS_NOTICE, "ME: HFS error : %d\n", errorcode);
//return 0;
}
me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48);
printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2);
printk(BIOS_NOTICE, "ME: Bist in progress: 0x%x\n", me_fws2 & 0x1);
printk(BIOS_NOTICE, "ME: ICC Status : 0x%x\n", (me_fws2 & 0x6) >> 1);
printk(BIOS_NOTICE, "ME: Invoke MEBx : 0x%x\n", (me_fws2 & 0x8) >> 3);
printk(BIOS_NOTICE, "ME: CPU replaced : 0x%x\n", (me_fws2 & 0x10) >> 4);
printk(BIOS_NOTICE, "ME: MBP ready : 0x%x\n", (me_fws2 & 0x20) >> 5);
printk(BIOS_NOTICE, "ME: MFS failure : 0x%x\n", (me_fws2 & 0x40) >> 6);
printk(BIOS_NOTICE, "ME: Warm reset req : 0x%x\n", (me_fws2 & 0x80) >> 7);
printk(BIOS_NOTICE, "ME: CPU repl valid : 0x%x\n", (me_fws2 & 0x100) >> 8);
printk(BIOS_NOTICE, "ME: (Reserved) : 0x%x\n", (me_fws2 & 0x600) >> 9);
printk(BIOS_NOTICE, "ME: FW update req : 0x%x\n", (me_fws2 & 0x800) >> 11);
printk(BIOS_NOTICE, "ME: (Reserved) : 0x%x\n", (me_fws2 & 0xf000) >> 12);
printk(BIOS_NOTICE, "ME: Current state : 0x%x\n", (me_fws2 & 0xff0000) >> 16);
printk(BIOS_NOTICE, "ME: Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24);
printk(BIOS_NOTICE, "ME: Progress code : 0x%x\n", (me_fws2 & 0xf0000000) >> 28);
// Poll cpu replaced for 50ms
millisec = 0;
while ((((me_fws2 & 0x100) >> 8) == 0) && millisec < 50) {
udelay(1000);
me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48);
millisec++;
}
if (millisec >= 50 || ((me_fws2 & 0x100) >> 8) == 0x0) {
printk(BIOS_NOTICE, "Waited long enough, or CPU was not replaced, continue...\n");
} else if ((me_fws2 & 0x100) == 0x100) {
if ((me_fws2 & 0x80) == 0x80) {
printk(BIOS_NOTICE, "CPU was replaced & warm reset required...\n");
reg16 = pcie_read_config16(PCI_DEV(0, 31, 0), 0xa2) & ~0x80;
pcie_write_config16(PCI_DEV(0, 31, 0), 0xa2, reg16);
set_global_reset(0);
outb(0x6, 0xcf9);
halt();
}
if (((me_fws2 & 0x10) == 0x10) && (me_fws2 & 0x80) == 0x00) {
printk(BIOS_NOTICE, "Full training required\n");
}
}
printk(BIOS_NOTICE, "PASSED! Tell ME that DRAM is ready\n");
/* MEBASE from MESEG_BASE[35:20] */
mebase_l = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_L);
mebase_h = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_H) & 0xf;
did.uma_base = (mebase_l >> 20) | (mebase_h << 12);
/* Send message to ME */
printk(BIOS_DEBUG, "ME: Sending Init Done with status: %d, "
"UMA base: 0x%04x\n", status, did.uma_base);
meDID = did.uma_base | (1 << 28);// | (1 << 23);
pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_ME_H_GS, meDID);
pci_write_dword_ptr(&did, PCI_ME_H_GS);
udelay(1100);
/* Must wait for ME acknowledgement */
for (count = ME_RETRY; count > 0; --count) {
pci_read_dword_ptr(&hfs, PCI_ME_HFS);
if (hfs.bios_msg_ack)
break;
udelay(ME_DELAY);
}
if (!count) {
printk(BIOS_ERR, "ERROR: ME failed to respond\n");
return -1;
millisec = 0;
hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xfe000000) >> 24;
while ((((hfs & 0xf0) >> 4) != ME_HFS_BIOS_DRAM_ACK) && (millisec < 5000)) {
udelay(1000);
hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xfe000000) >> 24;
millisec++;
}
me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48);
printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2);
printk(BIOS_NOTICE, "ME: Bist in progress: 0x%x\n", me_fws2 & 0x1);
printk(BIOS_NOTICE, "ME: ICC Status : 0x%x\n", (me_fws2 & 0x6) >> 1);
printk(BIOS_NOTICE, "ME: Invoke MEBx : 0x%x\n", (me_fws2 & 0x8) >> 3);
printk(BIOS_NOTICE, "ME: CPU replaced : 0x%x\n", (me_fws2 & 0x10) >> 4);
printk(BIOS_NOTICE, "ME: MBP ready : 0x%x\n", (me_fws2 & 0x20) >> 5);
printk(BIOS_NOTICE, "ME: MFS failure : 0x%x\n", (me_fws2 & 0x40) >> 6);
printk(BIOS_NOTICE, "ME: Warm reset req : 0x%x\n", (me_fws2 & 0x80) >> 7);
printk(BIOS_NOTICE, "ME: CPU repl valid : 0x%x\n", (me_fws2 & 0x100) >> 8);
printk(BIOS_NOTICE, "ME: (Reserved) : 0x%x\n", (me_fws2 & 0x600) >> 9);
printk(BIOS_NOTICE, "ME: FW update req : 0x%x\n", (me_fws2 & 0x800) >> 11);
printk(BIOS_NOTICE, "ME: (Reserved) : 0x%x\n", (me_fws2 & 0xf000) >> 12);
printk(BIOS_NOTICE, "ME: Current state : 0x%x\n", (me_fws2 & 0xff0000) >> 16);
printk(BIOS_NOTICE, "ME: Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24);
printk(BIOS_NOTICE, "ME: Progress code : 0x%x\n", (me_fws2 & 0xf0000000) >> 28);
/* Return the requested BIOS action */
printk(BIOS_NOTICE, "ME: Requested BIOS Action: %s\n",
me_ack_values[hfs.ack_data]);
me_ack_values[(hfs & 0xe) >> 1]);
/* Check status after acknowledgement */
intel_early_me_status();
reset = 0;
switch (hfs.ack_data) {
reset = inb(0xcf9);
reset &= 0xf1;
switch ((hfs & 0xe) >> 1) {
case ME_HFS_ACK_NO_DID:
case ME_HFS_ACK_CONTINUE:
/* Continue to boot */
return 0;
case ME_HFS_ACK_RESET:
/* Non-power cycle reset */
set_global_reset(0);
reset = 0x06;
reset |= 0x06;
break;
case ME_HFS_ACK_PWR_CYCLE:
/* Power cycle reset */
set_global_reset(0);
reset = 0x0e;
reset |= 0x0e;
break;
case ME_HFS_ACK_GBL_RESET:
/* Global reset */
set_global_reset(1);
reset = 0x0e;
reset |= 0x0e;
break;
case ME_HFS_ACK_S3:
case ME_HFS_ACK_S4:

199
src/southbridge/intel/bd82x6x/early_me_mrc.c Normal file
View File

@ -0,0 +1,199 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#include <arch/io.h>
#include <console/console.h>
#include <delay.h>
#include <device/pci_ids.h>
#include <halt.h>
#include <string.h>
#include "me.h"
#include "pch.h"
static const char *me_ack_values[] = {
[ME_HFS_ACK_NO_DID] = "No DID Ack received",
[ME_HFS_ACK_RESET] = "Non-power cycle reset",
[ME_HFS_ACK_PWR_CYCLE] = "Power cycle reset",
[ME_HFS_ACK_S3] = "Go to S3",
[ME_HFS_ACK_S4] = "Go to S4",
[ME_HFS_ACK_S5] = "Go to S5",
[ME_HFS_ACK_GBL_RESET] = "Global Reset",
[ME_HFS_ACK_CONTINUE] = "Continue to boot"
};
static inline void pci_read_dword_ptr(void *ptr, int offset)
{
u32 dword = pci_read_config32(PCH_ME_DEV, offset);
memcpy(ptr, &dword, sizeof(dword));
}
static inline void pci_write_dword_ptr(void *ptr, int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
pci_write_config32(PCH_ME_DEV, offset, dword);
}
void intel_early_me_status(void)
{
struct me_hfs hfs;
struct me_gmes gmes;
pci_read_dword_ptr(&hfs, PCI_ME_HFS);
pci_read_dword_ptr(&gmes, PCI_ME_GMES);
intel_me_status(&hfs, &gmes);
}
int intel_early_me_init(void)
{
int count;
struct me_uma uma;
struct me_hfs hfs;
printk(BIOS_INFO, "Intel ME early init\n");
/* Wait for ME UMA SIZE VALID bit to be set */
for (count = ME_RETRY; count > 0; --count) {
pci_read_dword_ptr(&uma, PCI_ME_UMA);
if (uma.valid)
break;
udelay(ME_DELAY);
}
if (!count) {
printk(BIOS_ERR, "ERROR: ME is not ready!\n");
return -1;
}
/* Check for valid firmware */
pci_read_dword_ptr(&hfs, PCI_ME_HFS);
if (hfs.fpt_bad) {
printk(BIOS_WARNING, "WARNING: ME has bad firmware\n");
return -1;
}
printk(BIOS_INFO, "Intel ME firmware is ready\n");
return 0;
}
int intel_early_me_uma_size(void)
{
struct me_uma uma;
pci_read_dword_ptr(&uma, PCI_ME_UMA);
if (uma.valid) {
printk(BIOS_DEBUG, "ME: Requested %uMB UMA\n", uma.size);
return uma.size;
}
printk(BIOS_DEBUG, "ME: Invalid UMA size\n");
return 0;
}
static inline void set_global_reset(int enable)
{
u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3);
/* Clear CF9 Without Resume Well Reset Enable */
etr3 &= ~ETR3_CWORWRE;
/* CF9GR indicates a Global Reset */
if (enable)
etr3 |= ETR3_CF9GR;
else
etr3 &= ~ETR3_CF9GR;
pci_write_config32(PCH_LPC_DEV, ETR3, etr3);
}
int intel_early_me_init_done(u8 status)
{
u8 reset;
int count;
u32 mebase_l, mebase_h;
struct me_hfs hfs;
struct me_did did = {
.init_done = ME_INIT_DONE,
.status = status
};
/* MEBASE from MESEG_BASE[35:20] */
mebase_l = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_L);
mebase_h = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_H) & 0xf;
did.uma_base = (mebase_l >> 20) | (mebase_h << 12);
/* Send message to ME */
printk(BIOS_DEBUG, "ME: Sending Init Done with status: %d, "
"UMA base: 0x%04x\n", status, did.uma_base);
pci_write_dword_ptr(&did, PCI_ME_H_GS);
/* Must wait for ME acknowledgement */
for (count = ME_RETRY; count > 0; --count) {
pci_read_dword_ptr(&hfs, PCI_ME_HFS);
if (hfs.bios_msg_ack)
break;
udelay(ME_DELAY);
}
if (!count) {
printk(BIOS_ERR, "ERROR: ME failed to respond\n");
return -1;
}
/* Return the requested BIOS action */
printk(BIOS_NOTICE, "ME: Requested BIOS Action: %s\n",
me_ack_values[hfs.ack_data]);
/* Check status after acknowledgement */
intel_early_me_status();
reset = 0;
switch (hfs.ack_data) {
case ME_HFS_ACK_CONTINUE:
/* Continue to boot */
return 0;
case ME_HFS_ACK_RESET:
/* Non-power cycle reset */
set_global_reset(0);
reset = 0x06;
break;
case ME_HFS_ACK_PWR_CYCLE:
/* Power cycle reset */
set_global_reset(0);
reset = 0x0e;
break;
case ME_HFS_ACK_GBL_RESET:
/* Global reset */
set_global_reset(1);
reset = 0x0e;
break;
case ME_HFS_ACK_S3:
case ME_HFS_ACK_S4:
case ME_HFS_ACK_S5:
break;
}
/* Perform the requested reset */
if (reset) {
outb(reset, 0xcf9);
halt();
}
return -1;
}

264
src/southbridge/intel/bd82x6x/early_me_native.c
View File

@ -1,264 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#include <arch/io.h>
#include <console/console.h>
#include <delay.h>
#include <device/pci_ids.h>
#include <halt.h>
#include <string.h>
#include "me.h"
#include "pch.h"
static const char *me_ack_values[] = {
[ME_HFS_ACK_NO_DID] = "No DID Ack received",
[ME_HFS_ACK_RESET] = "Non-power cycle reset",
[ME_HFS_ACK_PWR_CYCLE] = "Power cycle reset",
[ME_HFS_ACK_S3] = "Go to S3",
[ME_HFS_ACK_S4] = "Go to S4",
[ME_HFS_ACK_S5] = "Go to S5",
[ME_HFS_ACK_GBL_RESET] = "Global Reset",
[ME_HFS_ACK_CONTINUE] = "Continue to boot"
};
static inline void pci_read_dword_ptr(void *ptr, int offset)
{
u32 dword = pci_read_config32(PCH_ME_DEV, offset);
memcpy(ptr, &dword, sizeof(dword));
}
void intel_early_me_status(void)
{
struct me_hfs hfs;
struct me_gmes gmes;
pci_read_dword_ptr(&hfs, PCI_ME_HFS);
pci_read_dword_ptr(&gmes, PCI_ME_GMES);
intel_me_status(&hfs, &gmes);
}
int intel_early_me_init(void)
{
int count;
struct me_uma uma;
struct me_hfs hfs;
printk(BIOS_INFO, "Intel ME early init\n");
/* Wait for ME UMA SIZE VALID bit to be set */
for (count = ME_RETRY; count > 0; --count) {
pci_read_dword_ptr(&uma, PCI_ME_UMA);
if (uma.valid)
break;
udelay(ME_DELAY);
}
if (!count) {
printk(BIOS_ERR, "ERROR: ME is not ready!\n");
return -1;
}
/* Check for valid firmware */
pci_read_dword_ptr(&hfs, PCI_ME_HFS);
if (hfs.fpt_bad) {
printk(BIOS_WARNING, "WARNING: ME has bad firmware\n");
return -1;
}
printk(BIOS_INFO, "Intel ME firmware is ready\n");
return 0;
}
int intel_early_me_uma_size(void)
{
struct me_uma uma;
pci_read_dword_ptr(&uma, PCI_ME_UMA);
if (uma.valid) {
printk(BIOS_DEBUG, "ME: Requested %uMB UMA\n", uma.size);
return uma.size;
}
printk(BIOS_DEBUG, "ME: Invalid UMA size\n");
return 0;
}
static inline void set_global_reset(int enable)
{
u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3);
/* Clear CF9 Without Resume Well Reset Enable */
etr3 &= ~ETR3_CWORWRE;
/* CF9GR indicates a Global Reset */
if (enable)
etr3 |= ETR3_CF9GR;
else
etr3 &= ~ETR3_CF9GR;
pci_write_config32(PCH_LPC_DEV, ETR3, etr3);
}
int intel_early_me_init_done(u8 status)
{
u8 reset, errorcode, opmode;
u16 reg16;
u32 mebase_l, mebase_h;
u32 millisec;
u32 hfs, me_fws2;
struct me_did did = {
.init_done = ME_INIT_DONE,
.status = status
};
u32 meDID;
hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xff000) >> 12;
opmode = (hfs & 0xf0) >> 4;
errorcode = hfs & 0xf;
if (opmode != ME_HFS_MODE_NORMAL) {
printk(BIOS_NOTICE, "ME: Wrong mode : %d\n", opmode);
//return 0;
}
if (errorcode) {
printk(BIOS_NOTICE, "ME: HFS error : %d\n", errorcode);
//return 0;
}
me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48);
printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2);
printk(BIOS_NOTICE, "ME: Bist in progress: 0x%x\n", me_fws2 & 0x1);
printk(BIOS_NOTICE, "ME: ICC Status : 0x%x\n", (me_fws2 & 0x6) >> 1);
printk(BIOS_NOTICE, "ME: Invoke MEBx : 0x%x\n", (me_fws2 & 0x8) >> 3);
printk(BIOS_NOTICE, "ME: CPU replaced : 0x%x\n", (me_fws2 & 0x10) >> 4);
printk(BIOS_NOTICE, "ME: MBP ready : 0x%x\n", (me_fws2 & 0x20) >> 5);
printk(BIOS_NOTICE, "ME: MFS failure : 0x%x\n", (me_fws2 & 0x40) >> 6);
printk(BIOS_NOTICE, "ME: Warm reset req : 0x%x\n", (me_fws2 & 0x80) >> 7);
printk(BIOS_NOTICE, "ME: CPU repl valid : 0x%x\n", (me_fws2 & 0x100) >> 8);
printk(BIOS_NOTICE, "ME: (Reserved) : 0x%x\n", (me_fws2 & 0x600) >> 9);
printk(BIOS_NOTICE, "ME: FW update req : 0x%x\n", (me_fws2 & 0x800) >> 11);
printk(BIOS_NOTICE, "ME: (Reserved) : 0x%x\n", (me_fws2 & 0xf000) >> 12);
printk(BIOS_NOTICE, "ME: Current state : 0x%x\n", (me_fws2 & 0xff0000) >> 16);
printk(BIOS_NOTICE, "ME: Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24);
printk(BIOS_NOTICE, "ME: Progress code : 0x%x\n", (me_fws2 & 0xf0000000) >> 28);
// Poll cpu replaced for 50ms
millisec = 0;
while ((((me_fws2 & 0x100) >> 8) == 0) && millisec < 50) {
udelay(1000);
me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48);
millisec++;
}
if (millisec >= 50 || ((me_fws2 & 0x100) >> 8) == 0x0) {
printk(BIOS_NOTICE, "Waited long enough, or CPU was not replaced, continue...\n");
} else if ((me_fws2 & 0x100) == 0x100) {
if ((me_fws2 & 0x80) == 0x80) {
printk(BIOS_NOTICE, "CPU was replaced & warm reset required...\n");
reg16 = pcie_read_config16(PCI_DEV(0, 31, 0), 0xa2) & ~0x80;
pcie_write_config16(PCI_DEV(0, 31, 0), 0xa2, reg16);
set_global_reset(0);
outb(0x6, 0xcf9);
halt();
}
if (((me_fws2 & 0x10) == 0x10) && (me_fws2 & 0x80) == 0x00) {
printk(BIOS_NOTICE, "Full training required\n");
}
}
printk(BIOS_NOTICE, "PASSED! Tell ME that DRAM is ready\n");
/* MEBASE from MESEG_BASE[35:20] */
mebase_l = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_L);
mebase_h = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_H) & 0xf;
did.uma_base = (mebase_l >> 20) | (mebase_h << 12);
meDID = did.uma_base | (1 << 28);// | (1 << 23);
pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_ME_H_GS, meDID);
udelay(1100);
/* Must wait for ME acknowledgement */
millisec = 0;
hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xfe000000) >> 24;
while ((((hfs & 0xf0) >> 4) != ME_HFS_BIOS_DRAM_ACK) && (millisec < 5000)) {
udelay(1000);
hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xfe000000) >> 24;
millisec++;
}
me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48);
printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2);
printk(BIOS_NOTICE, "ME: Bist in progress: 0x%x\n", me_fws2 & 0x1);
printk(BIOS_NOTICE, "ME: ICC Status : 0x%x\n", (me_fws2 & 0x6) >> 1);
printk(BIOS_NOTICE, "ME: Invoke MEBx : 0x%x\n", (me_fws2 & 0x8) >> 3);
printk(BIOS_NOTICE, "ME: CPU replaced : 0x%x\n", (me_fws2 & 0x10) >> 4);
printk(BIOS_NOTICE, "ME: MBP ready : 0x%x\n", (me_fws2 & 0x20) >> 5);
printk(BIOS_NOTICE, "ME: MFS failure : 0x%x\n", (me_fws2 & 0x40) >> 6);
printk(BIOS_NOTICE, "ME: Warm reset req : 0x%x\n", (me_fws2 & 0x80) >> 7);
printk(BIOS_NOTICE, "ME: CPU repl valid : 0x%x\n", (me_fws2 & 0x100) >> 8);
printk(BIOS_NOTICE, "ME: (Reserved) : 0x%x\n", (me_fws2 & 0x600) >> 9);
printk(BIOS_NOTICE, "ME: FW update req : 0x%x\n", (me_fws2 & 0x800) >> 11);
printk(BIOS_NOTICE, "ME: (Reserved) : 0x%x\n", (me_fws2 & 0xf000) >> 12);
printk(BIOS_NOTICE, "ME: Current state : 0x%x\n", (me_fws2 & 0xff0000) >> 16);
printk(BIOS_NOTICE, "ME: Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24);
printk(BIOS_NOTICE, "ME: Progress code : 0x%x\n", (me_fws2 & 0xf0000000) >> 28);
/* Return the requested BIOS action */
printk(BIOS_NOTICE, "ME: Requested BIOS Action: %s\n",
me_ack_values[(hfs & 0xe) >> 1]);
reset = inb(0xcf9);
reset &= 0xf1;
switch ((hfs & 0xe) >> 1) {
case ME_HFS_ACK_NO_DID:
case ME_HFS_ACK_CONTINUE:
/* Continue to boot */
return 0;
case ME_HFS_ACK_RESET:
/* Non-power cycle reset */
set_global_reset(0);
reset |= 0x06;
break;
case ME_HFS_ACK_PWR_CYCLE:
/* Power cycle reset */
set_global_reset(0);
reset |= 0x0e;
break;
case ME_HFS_ACK_GBL_RESET:
/* Global reset */
set_global_reset(1);
reset |= 0x0e;
break;
case ME_HFS_ACK_S3:
case ME_HFS_ACK_S4:
case ME_HFS_ACK_S5:
break;
}
/* Perform the requested reset */
if (reset) {
outb(reset, 0xcf9);
halt();
}
return -1;
}

382
src/southbridge/intel/bd82x6x/early_pch.c
View File

@ -1,12 +1,11 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Vladimir Serbinenko <phcoder@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -18,45 +17,358 @@
* Foundation, Inc.
*/
#include <arch/io.h>
#include <timestamp.h>
#include <cpu/x86/tsc.h>
#include "pch.h"
#include <arch/acpi.h>
#include <console/console.h>
#include <string.h>
#include <arch/io.h>
#include <cbmem.h>
#include <arch/cbfs.h>
#include <cbfs.h>
#include <ip_checksum.h>
#include <pc80/mc146818rtc.h>
#include <device/pci_def.h>
#include <delay.h>
uint64_t get_initial_timestamp(void)
#include "pch.h"
/* For DMI bar. */
#include "northbridge/intel/sandybridge/sandybridge.h"
#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
static void
wait_2338 (void)
{
tsc_t base_time = {
.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
};
return tsc_to_uint64(base_time);
while (read8 (DEFAULT_RCBA + 0x2338) & 1);
}
int southbridge_detect_s3_resume(void)
static u32
read_2338 (u32 edx)
{
u32 pm1_cnt;
u16 pm1_sts;
u32 ret;
/* Check PM1_STS[15] to see if we are waking from Sx */
pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
write32 (DEFAULT_RCBA + 0x2330, edx);
write16 (DEFAULT_RCBA + 0x2338, (read16 (DEFAULT_RCBA + 0x2338)
& 0x1ff) | 0x600);
wait_2338 ();
ret = read32 (DEFAULT_RCBA + 0x2334);
wait_2338 ();
read8 (DEFAULT_RCBA + 0x2338);
return ret;
}
/* Read PM1_CNT[12:10] to determine which Sx state */
pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
static void
write_2338 (u32 edx, u32 val)
{
read_2338 (edx);
write16 (DEFAULT_RCBA + 0x2338, (read16 (DEFAULT_RCBA + 0x2338)
& 0x1ff) | 0x600);
wait_2338 ();
if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
if (acpi_s3_resume_allowed()) {
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
/* Clear SLP_TYPE. This will break stage2 but
* we care for that when we get there.
*/
outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
return 1;
} else {
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
}
write32 (DEFAULT_RCBA + 0x2334, val);
wait_2338 ();
write16 (DEFAULT_RCBA + 0x2338,
(read16 (DEFAULT_RCBA + 0x2338) & 0x1ff) | 0x600);
read8 (DEFAULT_RCBA + 0x2338);
}
static void
init_dmi (void)
{
int i;
write32 (DEFAULT_DMIBAR + 0x0914,
read32 (DEFAULT_DMIBAR + 0x0914) | 0x80000000);
write32 (DEFAULT_DMIBAR + 0x0934,
read32 (DEFAULT_DMIBAR + 0x0934) | 0x80000000);
for (i = 0; i < 4; i++)
{
write32 (DEFAULT_DMIBAR + 0x0a00 + (i << 4),
read32 (DEFAULT_DMIBAR + 0x0a00 + (i << 4)) & 0xf3ffffff);
write32 (DEFAULT_DMIBAR + 0x0a04 + (i << 4),
read32 (DEFAULT_DMIBAR + 0x0a04 + (i << 4)) | 0x800);
}
write32 (DEFAULT_DMIBAR + 0x0c30, (read32 (DEFAULT_DMIBAR + 0x0c30)
& 0xfffffff) | 0x40000000);
for (i = 0; i < 2; i++)
{
write32 (DEFAULT_DMIBAR + 0x0904 + (i << 5),
read32 (DEFAULT_DMIBAR + 0x0904 + (i << 5)) & 0xfe3fffff);
write32 (DEFAULT_DMIBAR + 0x090c + (i << 5),
read32 (DEFAULT_DMIBAR + 0x090c + (i << 5)) & 0xfff1ffff);
}
write32 (DEFAULT_DMIBAR + 0x090c,
read32 (DEFAULT_DMIBAR + 0x090c) & 0xfe1fffff);
write32 (DEFAULT_DMIBAR + 0x092c,
read32 (DEFAULT_DMIBAR + 0x092c) & 0xfe1fffff);
read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x7a1842ec
write32 (DEFAULT_DMIBAR + 0x0904, 0x7a1842ec);
read32 (DEFAULT_DMIBAR + 0x090c); // !!! = 0x00000208
write32 (DEFAULT_DMIBAR + 0x090c, 0x00000128);
read32 (DEFAULT_DMIBAR + 0x0924); // !!! = 0x7a1842ec
write32 (DEFAULT_DMIBAR + 0x0924, 0x7a1842ec);
read32 (DEFAULT_DMIBAR + 0x092c); // !!! = 0x00000208
write32 (DEFAULT_DMIBAR + 0x092c, 0x00000128);
read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x46139008
write32 (DEFAULT_DMIBAR + 0x0700, 0x46139008);
read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x46139008
write32 (DEFAULT_DMIBAR + 0x0720, 0x46139008);
read32 (DEFAULT_DMIBAR + 0x0c04); // !!! = 0x2e680008
write32 (DEFAULT_DMIBAR + 0x0c04, 0x2e680008);
read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x7a1842ec
write32 (DEFAULT_DMIBAR + 0x0904, 0x3a1842ec);
read32 (DEFAULT_DMIBAR + 0x0924); // !!! = 0x7a1842ec
write32 (DEFAULT_DMIBAR + 0x0924, 0x3a1842ec);
read32 (DEFAULT_DMIBAR + 0x0910); // !!! = 0x00006300
write32 (DEFAULT_DMIBAR + 0x0910, 0x00004300);
read32 (DEFAULT_DMIBAR + 0x0930); // !!! = 0x00006300
write32 (DEFAULT_DMIBAR + 0x0930, 0x00004300);
read32 (DEFAULT_DMIBAR + 0x0a00); // !!! = 0x03042010
write32 (DEFAULT_DMIBAR + 0x0a00, 0x03042018);
read32 (DEFAULT_DMIBAR + 0x0a10); // !!! = 0x03042010
write32 (DEFAULT_DMIBAR + 0x0a10, 0x03042018);
read32 (DEFAULT_DMIBAR + 0x0a20); // !!! = 0x03042010
write32 (DEFAULT_DMIBAR + 0x0a20, 0x03042018);
read32 (DEFAULT_DMIBAR + 0x0a30); // !!! = 0x03042010
write32 (DEFAULT_DMIBAR + 0x0a30, 0x03042018);
read32 (DEFAULT_DMIBAR + 0x0c00); // !!! = 0x29700c08
write32 (DEFAULT_DMIBAR + 0x0c00, 0x29700c08);
read32 (DEFAULT_DMIBAR + 0x0a04); // !!! = 0x0c0708f0
write32 (DEFAULT_DMIBAR + 0x0a04, 0x0c0718f0);
read32 (DEFAULT_DMIBAR + 0x0a14); // !!! = 0x0c0708f0
write32 (DEFAULT_DMIBAR + 0x0a14, 0x0c0718f0);
read32 (DEFAULT_DMIBAR + 0x0a24); // !!! = 0x0c0708f0
write32 (DEFAULT_DMIBAR + 0x0a24, 0x0c0718f0);
read32 (DEFAULT_DMIBAR + 0x0a34); // !!! = 0x0c0708f0
write32 (DEFAULT_DMIBAR + 0x0a34, 0x0c0718f0);
read32 (DEFAULT_DMIBAR + 0x0900); // !!! = 0x50000000
write32 (DEFAULT_DMIBAR + 0x0900, 0x50000000);
read32 (DEFAULT_DMIBAR + 0x0920); // !!! = 0x50000000
write32 (DEFAULT_DMIBAR + 0x0920, 0x50000000);
read32 (DEFAULT_DMIBAR + 0x0908); // !!! = 0x51ffffff
write32 (DEFAULT_DMIBAR + 0x0908, 0x51ffffff);
read32 (DEFAULT_DMIBAR + 0x0928); // !!! = 0x51ffffff
write32 (DEFAULT_DMIBAR + 0x0928, 0x51ffffff);
read32 (DEFAULT_DMIBAR + 0x0a00); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR + 0x0a00, 0x03042018);
read32 (DEFAULT_DMIBAR + 0x0a10); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR + 0x0a10, 0x03042018);
read32 (DEFAULT_DMIBAR + 0x0a20); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR + 0x0a20, 0x03042018);
read32 (DEFAULT_DMIBAR + 0x0a30); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR + 0x0a30, 0x03042018);
read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x46139008
write32 (DEFAULT_DMIBAR + 0x0700, 0x46139008);
read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x46139008
write32 (DEFAULT_DMIBAR + 0x0720, 0x46139008);
read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x3a1842ec
write32 (DEFAULT_DMIBAR + 0x0904, 0x3a1846ec);
read32 (DEFAULT_DMIBAR + 0x0924); // !!! = 0x3a1842ec
write32 (DEFAULT_DMIBAR + 0x0924, 0x3a1846ec);
read32 (DEFAULT_DMIBAR + 0x0a00); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR + 0x0a00, 0x03042018);
read32 (DEFAULT_DMIBAR + 0x0a10); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR + 0x0a10, 0x03042018);
read32 (DEFAULT_DMIBAR + 0x0a20); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR + 0x0a20, 0x03042018);
read32 (DEFAULT_DMIBAR + 0x0a30); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR + 0x0a30, 0x03042018);
read32 (DEFAULT_DMIBAR + 0x0908); // !!! = 0x51ffffff
write32 (DEFAULT_DMIBAR + 0x0908, 0x51ffffff);
read32 (DEFAULT_DMIBAR + 0x0928); // !!! = 0x51ffffff
write32 (DEFAULT_DMIBAR + 0x0928, 0x51ffffff);
read32 (DEFAULT_DMIBAR + 0x0c00); // !!! = 0x29700c08
write32 (DEFAULT_DMIBAR + 0x0c00, 0x29700c08);
read32 (DEFAULT_DMIBAR + 0x0c0c); // !!! = 0x16063400
write32 (DEFAULT_DMIBAR + 0x0c0c, 0x00063400);
read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x46139008
write32 (DEFAULT_DMIBAR + 0x0700, 0x46339008);
read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x46139008
write32 (DEFAULT_DMIBAR + 0x0720, 0x46339008);
read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x46339008
write32 (DEFAULT_DMIBAR + 0x0700, 0x45339008);
read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x46339008
write32 (DEFAULT_DMIBAR + 0x0720, 0x45339008);
read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x45339008
write32 (DEFAULT_DMIBAR + 0x0700, 0x453b9008);
read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x45339008
write32 (DEFAULT_DMIBAR + 0x0720, 0x453b9008);
read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x453b9008
write32 (DEFAULT_DMIBAR + 0x0700, 0x45bb9008);
read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x453b9008
write32 (DEFAULT_DMIBAR + 0x0720, 0x45bb9008);
read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x45bb9008
write32 (DEFAULT_DMIBAR + 0x0700, 0x45fb9008);
read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x45bb9008
write32 (DEFAULT_DMIBAR + 0x0720, 0x45fb9008);
read32 (DEFAULT_DMIBAR + 0x0914); // !!! = 0x9021a080
write32 (DEFAULT_DMIBAR + 0x0914, 0x9021a280);
read32 (DEFAULT_DMIBAR + 0x0934); // !!! = 0x9021a080
write32 (DEFAULT_DMIBAR + 0x0934, 0x9021a280);
read32 (DEFAULT_DMIBAR + 0x0914); // !!! = 0x9021a280
write32 (DEFAULT_DMIBAR + 0x0914, 0x9821a280);
read32 (DEFAULT_DMIBAR + 0x0934); // !!! = 0x9021a280
write32 (DEFAULT_DMIBAR + 0x0934, 0x9821a280);
read32 (DEFAULT_DMIBAR + 0x0a00); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR + 0x0a00, 0x03242018);
read32 (DEFAULT_DMIBAR + 0x0a10); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR + 0x0a10, 0x03242018);
read32 (DEFAULT_DMIBAR + 0x0a20); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR + 0x0a20, 0x03242018);
read32 (DEFAULT_DMIBAR + 0x0a30); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR + 0x0a30, 0x03242018);
read32 (DEFAULT_DMIBAR + 0x0258); // !!! = 0x40000600
write32 (DEFAULT_DMIBAR + 0x0258, 0x60000600);
read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x3a1846ec
write32 (DEFAULT_DMIBAR + 0x0904, 0x2a1846ec);
read32 (DEFAULT_DMIBAR + 0x0914); // !!! = 0x9821a280
write32 (DEFAULT_DMIBAR + 0x0914, 0x98200280);
read32 (DEFAULT_DMIBAR + 0x0924); // !!! = 0x3a1846ec
write32 (DEFAULT_DMIBAR + 0x0924, 0x2a1846ec);
read32 (DEFAULT_DMIBAR + 0x0934); // !!! = 0x9821a280
write32 (DEFAULT_DMIBAR + 0x0934, 0x98200280);
read32 (DEFAULT_DMIBAR + 0x022c); // !!! = 0x00c26460
write32 (DEFAULT_DMIBAR + 0x022c, 0x00c2403c);
read8 (DEFAULT_RCBA + 0x21a4); // !!! = 0x42
return 0;
read32 (DEFAULT_RCBA + 0x21a4); // !!! = 0x00012c42
read32 (DEFAULT_RCBA + 0x2340); // !!! = 0x0013001b
write32 (DEFAULT_RCBA + 0x2340, 0x003a001b);
read8 (DEFAULT_RCBA + 0x21b0); // !!! = 0x01
write8 (DEFAULT_RCBA + 0x21b0, 0x02);
read32 (DEFAULT_DMIBAR + 0x0084); // !!! = 0x0041ac41
write32 (DEFAULT_DMIBAR + 0x0084, 0x0041ac42);
read8 (DEFAULT_DMIBAR + 0x0088); // !!! = 0x00
write8 (DEFAULT_DMIBAR + 0x0088, 0x20);
read16 (DEFAULT_DMIBAR + 0x008a); // !!! = 0x0041
read8 (DEFAULT_DMIBAR + 0x0088); // !!! = 0x00
write8 (DEFAULT_DMIBAR + 0x0088, 0x20);
read16 (DEFAULT_DMIBAR + 0x008a); // !!! = 0x0042
read16 (DEFAULT_DMIBAR + 0x008a); // !!! = 0x0042
read32 (DEFAULT_DMIBAR + 0x0014); // !!! = 0x8000007f
write32 (DEFAULT_DMIBAR + 0x0014, 0x80000019);
read32 (DEFAULT_DMIBAR + 0x0020); // !!! = 0x01000000
write32 (DEFAULT_DMIBAR + 0x0020, 0x81000022);
read32 (DEFAULT_DMIBAR + 0x002c); // !!! = 0x02000000
write32 (DEFAULT_DMIBAR + 0x002c, 0x82000044);
read32 (DEFAULT_DMIBAR + 0x0038); // !!! = 0x07000080
write32 (DEFAULT_DMIBAR + 0x0038, 0x87000080);
read8 (DEFAULT_DMIBAR + 0x0004); // !!! = 0x00
write8 (DEFAULT_DMIBAR + 0x0004, 0x01);
read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x01200654
write32 (DEFAULT_RCBA + 0x0050, 0x01200654);
read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x01200654
write32 (DEFAULT_RCBA + 0x0050, 0x012a0654);
read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x012a0654
read8 (DEFAULT_RCBA + 0x1114); // !!! = 0x00
write8 (DEFAULT_RCBA + 0x1114, 0x05);
read32 (DEFAULT_RCBA + 0x2014); // !!! = 0x80000011
write32 (DEFAULT_RCBA + 0x2014, 0x80000019);
read32 (DEFAULT_RCBA + 0x2020); // !!! = 0x00000000
write32 (DEFAULT_RCBA + 0x2020, 0x81000022);
read32 (DEFAULT_RCBA + 0x2020); // !!! = 0x81000022
read32 (DEFAULT_RCBA + 0x2030); // !!! = 0x00000000
write32 (DEFAULT_RCBA + 0x2030, 0x82000044);
read32 (DEFAULT_RCBA + 0x2030); // !!! = 0x82000044
read32 (DEFAULT_RCBA + 0x2040); // !!! = 0x00000000
write32 (DEFAULT_RCBA + 0x2040, 0x87000080);
read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x012a0654
write32 (DEFAULT_RCBA + 0x0050, 0x812a0654);
read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x812a0654
read16 (DEFAULT_RCBA + 0x201a); // !!! = 0x0000
read16 (DEFAULT_RCBA + 0x2026); // !!! = 0x0000
read16 (DEFAULT_RCBA + 0x2036); // !!! = 0x0000
read16 (DEFAULT_RCBA + 0x2046); // !!! = 0x0000
read16 (DEFAULT_DMIBAR + 0x001a); // !!! = 0x0000
read16 (DEFAULT_DMIBAR + 0x0026); // !!! = 0x0000
read16 (DEFAULT_DMIBAR + 0x0032); // !!! = 0x0000
read16 (DEFAULT_DMIBAR + 0x003e); // !!! = 0x0000
}
void
early_pch_init_native (void)
{
pcie_write_config8 (SOUTHBRIDGE, 0xa6,
pcie_read_config8 (SOUTHBRIDGE, 0xa6) | 2);
write32 (DEFAULT_RCBA + 0x2088, 0x00109000);
read32 (DEFAULT_RCBA + 0x20ac); // !!! = 0x00000000
write32 (DEFAULT_RCBA + 0x20ac, 0x40000000);
write32 (DEFAULT_RCBA + 0x100c, 0x01110000);
write8 (DEFAULT_RCBA + 0x2340, 0x1b);
read32 (DEFAULT_RCBA + 0x2314); // !!! = 0x0a080000
write32 (DEFAULT_RCBA + 0x2314, 0x0a280000);
read32 (DEFAULT_RCBA + 0x2310); // !!! = 0xc809605b
write32 (DEFAULT_RCBA + 0x2310, 0xa809605b);
write32 (DEFAULT_RCBA + 0x2324, 0x00854c74);
read8 (DEFAULT_RCBA + 0x0400); // !!! = 0x00
read32 (DEFAULT_RCBA + 0x2310); // !!! = 0xa809605b
write32 (DEFAULT_RCBA + 0x2310, 0xa809605b);
read32 (DEFAULT_RCBA + 0x2310); // !!! = 0xa809605b
write32 (DEFAULT_RCBA + 0x2310, 0xa809605b);
write_2338 (0xea007f62, 0x00590133);
write_2338 (0xec007f62, 0x00590133);
write_2338 (0xec007f64, 0x59555588);
write_2338 (0xea0040b9, 0x0001051c);
write_2338 (0xeb0040a1, 0x800084ff);
write_2338 (0xec0040a1, 0x800084ff);
write_2338 (0xea004001, 0x00008400);
write_2338 (0xeb004002, 0x40201758);
write_2338 (0xec004002, 0x40201758);
write_2338 (0xea004002, 0x00601758);
write_2338 (0xea0040a1, 0x810084ff);
write_2338 (0xeb0040b1, 0x0001c598);
write_2338 (0xec0040b1, 0x0001c598);
write_2338 (0xeb0040b6, 0x0001c598);
write_2338 (0xea0000a9, 0x80ff969f);
write_2338 (0xea0001a9, 0x80ff969f);
write_2338 (0xeb0040b2, 0x0001c396);
write_2338 (0xeb0040b3, 0x0001c396);
write_2338 (0xec0040b2, 0x0001c396);
write_2338 (0xea0001a9, 0x80ff94ff);
write_2338 (0xea000151, 0x0088037f);
write_2338 (0xea0000a9, 0x80ff94ff);
write_2338 (0xea000051, 0x0088037f);
write_2338 (0xea007f05, 0x00010642);
write_2338 (0xea0040b7, 0x0001c91c);
write_2338 (0xea0040b8, 0x0001c91c);
write_2338 (0xeb0040a1, 0x820084ff);
write_2338 (0xec0040a1, 0x820084ff);
write_2338 (0xea007f0a, 0xc2480000);
write_2338 (0xec00404d, 0x1ff177f);
write_2338 (0xec000084, 0x5a600000);
write_2338 (0xec000184, 0x5a600000);
write_2338 (0xec000284, 0x5a600000);
write_2338 (0xec000384, 0x5a600000);
write_2338 (0xec000094, 0x000f0501);
write_2338 (0xec000194, 0x000f0501);
write_2338 (0xec000294, 0x000f0501);
write_2338 (0xec000394, 0x000f0501);
write_2338 (0xec000096, 0x00000001);
write_2338 (0xec000196, 0x00000001);
write_2338 (0xec000296, 0x00000001);
write_2338 (0xec000396, 0x00000001);
write_2338 (0xec000001, 0x00008c08);
write_2338 (0xec000101, 0x00008c08);
write_2338 (0xec000201, 0x00008c08);
write_2338 (0xec000301, 0x00008c08);
write_2338 (0xec0040b5, 0x0001c518);
write_2338 (0xec000087, 0x06077597);
write_2338 (0xec000187, 0x06077597);
write_2338 (0xec000287, 0x06077597);
write_2338 (0xec000387, 0x06077597);
write_2338 (0xea000050, 0x00bb0157);
write_2338 (0xea000150, 0x00bb0157);
write_2338 (0xec007f60, 0x77777d77);
write_2338 (0xea00008d, 0x01320000);
write_2338 (0xea00018d, 0x01320000);
write_2338 (0xec0007b2, 0x04514b5e);
write_2338 (0xec00078c, 0x40000200);
write_2338 (0xec000780, 0x02000020);
init_dmi();
}

62
src/southbridge/intel/bd82x6x/early_pch_common.c Normal file
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@ -0,0 +1,62 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#include <arch/io.h>
#include <timestamp.h>
#include <cpu/x86/tsc.h>
#include "pch.h"
#include <arch/acpi.h>
#include <console/console.h>
uint64_t get_initial_timestamp(void)
{
tsc_t base_time = {
.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
};
return tsc_to_uint64(base_time);
}
int southbridge_detect_s3_resume(void)
{
u32 pm1_cnt;
u16 pm1_sts;
/* Check PM1_STS[15] to see if we are waking from Sx */
pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
/* Read PM1_CNT[12:10] to determine which Sx state */
pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
if (acpi_s3_resume_allowed()) {
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
/* Clear SLP_TYPE. This will break stage2 but
* we care for that when we get there.
*/
outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
return 1;
} else {
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
}
}
return 0;
}

374
src/southbridge/intel/bd82x6x/early_pch_native.c
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@ -1,374 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Vladimir Serbinenko <phcoder@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#include <console/console.h>
#include <string.h>
#include <arch/io.h>
#include <cbmem.h>
#include <arch/cbfs.h>
#include <cbfs.h>
#include <ip_checksum.h>
#include <pc80/mc146818rtc.h>
#include <device/pci_def.h>
#include <delay.h>
#include "pch.h"
/* For DMI bar. */
#include "northbridge/intel/sandybridge/sandybridge.h"
#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
static void
wait_2338 (void)
{
while (read8 (DEFAULT_RCBA + 0x2338) & 1);
}
static u32
read_2338 (u32 edx)
{
u32 ret;
write32 (DEFAULT_RCBA + 0x2330, edx);
write16 (DEFAULT_RCBA + 0x2338, (read16 (DEFAULT_RCBA + 0x2338)
& 0x1ff) | 0x600);
wait_2338 ();
ret = read32 (DEFAULT_RCBA + 0x2334);
wait_2338 ();
read8 (DEFAULT_RCBA + 0x2338);
return ret;
}
static void
write_2338 (u32 edx, u32 val)
{
read_2338 (edx);
write16 (DEFAULT_RCBA + 0x2338, (read16 (DEFAULT_RCBA + 0x2338)
& 0x1ff) | 0x600);
wait_2338 ();
write32 (DEFAULT_RCBA + 0x2334, val);
wait_2338 ();
write16 (DEFAULT_RCBA + 0x2338,
(read16 (DEFAULT_RCBA + 0x2338) & 0x1ff) | 0x600);
read8 (DEFAULT_RCBA + 0x2338);
}
static void
init_dmi (void)
{
int i;
write32 (DEFAULT_DMIBAR + 0x0914,
read32 (DEFAULT_DMIBAR + 0x0914) | 0x80000000);
write32 (DEFAULT_DMIBAR + 0x0934,
read32 (DEFAULT_DMIBAR + 0x0934) | 0x80000000);
for (i = 0; i < 4; i++)
{
write32 (DEFAULT_DMIBAR + 0x0a00 + (i << 4),
read32 (DEFAULT_DMIBAR + 0x0a00 + (i << 4)) & 0xf3ffffff);
write32 (DEFAULT_DMIBAR + 0x0a04 + (i << 4),
read32 (DEFAULT_DMIBAR + 0x0a04 + (i << 4)) | 0x800);
}
write32 (DEFAULT_DMIBAR + 0x0c30, (read32 (DEFAULT_DMIBAR + 0x0c30)
& 0xfffffff) | 0x40000000);
for (i = 0; i < 2; i++)
{
write32 (DEFAULT_DMIBAR + 0x0904 + (i << 5),
read32 (DEFAULT_DMIBAR + 0x0904 + (i << 5)) & 0xfe3fffff);
write32 (DEFAULT_DMIBAR + 0x090c + (i << 5),
read32 (DEFAULT_DMIBAR + 0x090c + (i << 5)) & 0xfff1ffff);
}
write32 (DEFAULT_DMIBAR + 0x090c,
read32 (DEFAULT_DMIBAR + 0x090c) & 0xfe1fffff);
write32 (DEFAULT_DMIBAR + 0x092c,
read32 (DEFAULT_DMIBAR + 0x092c) & 0xfe1fffff);
read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x7a1842ec
write32 (DEFAULT_DMIBAR + 0x0904, 0x7a1842ec);
read32 (DEFAULT_DMIBAR + 0x090c); // !!! = 0x00000208
write32 (DEFAULT_DMIBAR + 0x090c, 0x00000128);
read32 (DEFAULT_DMIBAR + 0x0924); // !!! = 0x7a1842ec
write32 (DEFAULT_DMIBAR + 0x0924, 0x7a1842ec);
read32 (DEFAULT_DMIBAR + 0x092c); // !!! = 0x00000208
write32 (DEFAULT_DMIBAR + 0x092c, 0x00000128);
read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x46139008
write32 (DEFAULT_DMIBAR + 0x0700, 0x46139008);
read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x46139008
write32 (DEFAULT_DMIBAR + 0x0720, 0x46139008);
read32 (DEFAULT_DMIBAR + 0x0c04); // !!! = 0x2e680008
write32 (DEFAULT_DMIBAR + 0x0c04, 0x2e680008);
read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x7a1842ec
write32 (DEFAULT_DMIBAR + 0x0904, 0x3a1842ec);
read32 (DEFAULT_DMIBAR + 0x0924); // !!! = 0x7a1842ec
write32 (DEFAULT_DMIBAR + 0x0924, 0x3a1842ec);
read32 (DEFAULT_DMIBAR + 0x0910); // !!! = 0x00006300
write32 (DEFAULT_DMIBAR + 0x0910, 0x00004300);
read32 (DEFAULT_DMIBAR + 0x0930); // !!! = 0x00006300
write32 (DEFAULT_DMIBAR + 0x0930, 0x00004300);
read32 (DEFAULT_DMIBAR + 0x0a00); // !!! = 0x03042010
write32 (DEFAULT_DMIBAR + 0x0a00, 0x03042018);
read32 (DEFAULT_DMIBAR + 0x0a10); // !!! = 0x03042010
write32 (DEFAULT_DMIBAR + 0x0a10, 0x03042018);
read32 (DEFAULT_DMIBAR + 0x0a20); // !!! = 0x03042010
write32 (DEFAULT_DMIBAR + 0x0a20, 0x03042018);
read32 (DEFAULT_DMIBAR + 0x0a30); // !!! = 0x03042010
write32 (DEFAULT_DMIBAR + 0x0a30, 0x03042018);
read32 (DEFAULT_DMIBAR + 0x0c00); // !!! = 0x29700c08
write32 (DEFAULT_DMIBAR + 0x0c00, 0x29700c08);
read32 (DEFAULT_DMIBAR + 0x0a04); // !!! = 0x0c0708f0
write32 (DEFAULT_DMIBAR + 0x0a04, 0x0c0718f0);
read32 (DEFAULT_DMIBAR + 0x0a14); // !!! = 0x0c0708f0
write32 (DEFAULT_DMIBAR + 0x0a14, 0x0c0718f0);
read32 (DEFAULT_DMIBAR + 0x0a24); // !!! = 0x0c0708f0
write32 (DEFAULT_DMIBAR + 0x0a24, 0x0c0718f0);
read32 (DEFAULT_DMIBAR + 0x0a34); // !!! = 0x0c0708f0
write32 (DEFAULT_DMIBAR + 0x0a34, 0x0c0718f0);
read32 (DEFAULT_DMIBAR + 0x0900); // !!! = 0x50000000
write32 (DEFAULT_DMIBAR + 0x0900, 0x50000000);
read32 (DEFAULT_DMIBAR + 0x0920); // !!! = 0x50000000
write32 (DEFAULT_DMIBAR + 0x0920, 0x50000000);
read32 (DEFAULT_DMIBAR + 0x0908); // !!! = 0x51ffffff
write32 (DEFAULT_DMIBAR + 0x0908, 0x51ffffff);
read32 (DEFAULT_DMIBAR + 0x0928); // !!! = 0x51ffffff
write32 (DEFAULT_DMIBAR + 0x0928, 0x51ffffff);
read32 (DEFAULT_DMIBAR + 0x0a00); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR + 0x0a00, 0x03042018);
read32 (DEFAULT_DMIBAR + 0x0a10); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR + 0x0a10, 0x03042018);
read32 (DEFAULT_DMIBAR + 0x0a20); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR + 0x0a20, 0x03042018);
read32 (DEFAULT_DMIBAR + 0x0a30); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR + 0x0a30, 0x03042018);
read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x46139008
write32 (DEFAULT_DMIBAR + 0x0700, 0x46139008);
read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x46139008
write32 (DEFAULT_DMIBAR + 0x0720, 0x46139008);
read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x3a1842ec
write32 (DEFAULT_DMIBAR + 0x0904, 0x3a1846ec);
read32 (DEFAULT_DMIBAR + 0x0924); // !!! = 0x3a1842ec
write32 (DEFAULT_DMIBAR + 0x0924, 0x3a1846ec);
read32 (DEFAULT_DMIBAR + 0x0a00); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR + 0x0a00, 0x03042018);
read32 (DEFAULT_DMIBAR + 0x0a10); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR + 0x0a10, 0x03042018);
read32 (DEFAULT_DMIBAR + 0x0a20); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR + 0x0a20, 0x03042018);
read32 (DEFAULT_DMIBAR + 0x0a30); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR + 0x0a30, 0x03042018);
read32 (DEFAULT_DMIBAR + 0x0908); // !!! = 0x51ffffff
write32 (DEFAULT_DMIBAR + 0x0908, 0x51ffffff);
read32 (DEFAULT_DMIBAR + 0x0928); // !!! = 0x51ffffff
write32 (DEFAULT_DMIBAR + 0x0928, 0x51ffffff);
read32 (DEFAULT_DMIBAR + 0x0c00); // !!! = 0x29700c08
write32 (DEFAULT_DMIBAR + 0x0c00, 0x29700c08);
read32 (DEFAULT_DMIBAR + 0x0c0c); // !!! = 0x16063400
write32 (DEFAULT_DMIBAR + 0x0c0c, 0x00063400);
read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x46139008
write32 (DEFAULT_DMIBAR + 0x0700, 0x46339008);
read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x46139008
write32 (DEFAULT_DMIBAR + 0x0720, 0x46339008);
read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x46339008
write32 (DEFAULT_DMIBAR + 0x0700, 0x45339008);
read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x46339008
write32 (DEFAULT_DMIBAR + 0x0720, 0x45339008);
read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x45339008
write32 (DEFAULT_DMIBAR + 0x0700, 0x453b9008);
read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x45339008
write32 (DEFAULT_DMIBAR + 0x0720, 0x453b9008);
read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x453b9008
write32 (DEFAULT_DMIBAR + 0x0700, 0x45bb9008);
read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x453b9008
write32 (DEFAULT_DMIBAR + 0x0720, 0x45bb9008);
read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x45bb9008
write32 (DEFAULT_DMIBAR + 0x0700, 0x45fb9008);
read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x45bb9008
write32 (DEFAULT_DMIBAR + 0x0720, 0x45fb9008);
read32 (DEFAULT_DMIBAR + 0x0914); // !!! = 0x9021a080
write32 (DEFAULT_DMIBAR + 0x0914, 0x9021a280);
read32 (DEFAULT_DMIBAR + 0x0934); // !!! = 0x9021a080
write32 (DEFAULT_DMIBAR + 0x0934, 0x9021a280);
read32 (DEFAULT_DMIBAR + 0x0914); // !!! = 0x9021a280
write32 (DEFAULT_DMIBAR + 0x0914, 0x9821a280);
read32 (DEFAULT_DMIBAR + 0x0934); // !!! = 0x9021a280
write32 (DEFAULT_DMIBAR + 0x0934, 0x9821a280);
read32 (DEFAULT_DMIBAR + 0x0a00); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR + 0x0a00, 0x03242018);
read32 (DEFAULT_DMIBAR + 0x0a10); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR + 0x0a10, 0x03242018);
read32 (DEFAULT_DMIBAR + 0x0a20); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR + 0x0a20, 0x03242018);
read32 (DEFAULT_DMIBAR + 0x0a30); // !!! = 0x03042018
write32 (DEFAULT_DMIBAR + 0x0a30, 0x03242018);
read32 (DEFAULT_DMIBAR + 0x0258); // !!! = 0x40000600
write32 (DEFAULT_DMIBAR + 0x0258, 0x60000600);
read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x3a1846ec
write32 (DEFAULT_DMIBAR + 0x0904, 0x2a1846ec);
read32 (DEFAULT_DMIBAR + 0x0914); // !!! = 0x9821a280
write32 (DEFAULT_DMIBAR + 0x0914, 0x98200280);
read32 (DEFAULT_DMIBAR + 0x0924); // !!! = 0x3a1846ec
write32 (DEFAULT_DMIBAR + 0x0924, 0x2a1846ec);
read32 (DEFAULT_DMIBAR + 0x0934); // !!! = 0x9821a280
write32 (DEFAULT_DMIBAR + 0x0934, 0x98200280);
read32 (DEFAULT_DMIBAR + 0x022c); // !!! = 0x00c26460
write32 (DEFAULT_DMIBAR + 0x022c, 0x00c2403c);
read8 (DEFAULT_RCBA + 0x21a4); // !!! = 0x42
read32 (DEFAULT_RCBA + 0x21a4); // !!! = 0x00012c42
read32 (DEFAULT_RCBA + 0x2340); // !!! = 0x0013001b
write32 (DEFAULT_RCBA + 0x2340, 0x003a001b);
read8 (DEFAULT_RCBA + 0x21b0); // !!! = 0x01
write8 (DEFAULT_RCBA + 0x21b0, 0x02);
read32 (DEFAULT_DMIBAR + 0x0084); // !!! = 0x0041ac41
write32 (DEFAULT_DMIBAR + 0x0084, 0x0041ac42);
read8 (DEFAULT_DMIBAR + 0x0088); // !!! = 0x00
write8 (DEFAULT_DMIBAR + 0x0088, 0x20);
read16 (DEFAULT_DMIBAR + 0x008a); // !!! = 0x0041
read8 (DEFAULT_DMIBAR + 0x0088); // !!! = 0x00
write8 (DEFAULT_DMIBAR + 0x0088, 0x20);
read16 (DEFAULT_DMIBAR + 0x008a); // !!! = 0x0042
read16 (DEFAULT_DMIBAR + 0x008a); // !!! = 0x0042
read32 (DEFAULT_DMIBAR + 0x0014); // !!! = 0x8000007f
write32 (DEFAULT_DMIBAR + 0x0014, 0x80000019);
read32 (DEFAULT_DMIBAR + 0x0020); // !!! = 0x01000000
write32 (DEFAULT_DMIBAR + 0x0020, 0x81000022);
read32 (DEFAULT_DMIBAR + 0x002c); // !!! = 0x02000000
write32 (DEFAULT_DMIBAR + 0x002c, 0x82000044);
read32 (DEFAULT_DMIBAR + 0x0038); // !!! = 0x07000080
write32 (DEFAULT_DMIBAR + 0x0038, 0x87000080);
read8 (DEFAULT_DMIBAR + 0x0004); // !!! = 0x00
write8 (DEFAULT_DMIBAR + 0x0004, 0x01);
read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x01200654
write32 (DEFAULT_RCBA + 0x0050, 0x01200654);
read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x01200654
write32 (DEFAULT_RCBA + 0x0050, 0x012a0654);
read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x012a0654
read8 (DEFAULT_RCBA + 0x1114); // !!! = 0x00
write8 (DEFAULT_RCBA + 0x1114, 0x05);
read32 (DEFAULT_RCBA + 0x2014); // !!! = 0x80000011
write32 (DEFAULT_RCBA + 0x2014, 0x80000019);
read32 (DEFAULT_RCBA + 0x2020); // !!! = 0x00000000
write32 (DEFAULT_RCBA + 0x2020, 0x81000022);
read32 (DEFAULT_RCBA + 0x2020); // !!! = 0x81000022
read32 (DEFAULT_RCBA + 0x2030); // !!! = 0x00000000
write32 (DEFAULT_RCBA + 0x2030, 0x82000044);
read32 (DEFAULT_RCBA + 0x2030); // !!! = 0x82000044
read32 (DEFAULT_RCBA + 0x2040); // !!! = 0x00000000
write32 (DEFAULT_RCBA + 0x2040, 0x87000080);
read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x012a0654
write32 (DEFAULT_RCBA + 0x0050, 0x812a0654);
read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x812a0654
read16 (DEFAULT_RCBA + 0x201a); // !!! = 0x0000
read16 (DEFAULT_RCBA + 0x2026); // !!! = 0x0000
read16 (DEFAULT_RCBA + 0x2036); // !!! = 0x0000
read16 (DEFAULT_RCBA + 0x2046); // !!! = 0x0000
read16 (DEFAULT_DMIBAR + 0x001a); // !!! = 0x0000
read16 (DEFAULT_DMIBAR + 0x0026); // !!! = 0x0000
read16 (DEFAULT_DMIBAR + 0x0032); // !!! = 0x0000
read16 (DEFAULT_DMIBAR + 0x003e); // !!! = 0x0000
}
void
early_pch_init_native (void)
{
pcie_write_config8 (SOUTHBRIDGE, 0xa6,
pcie_read_config8 (SOUTHBRIDGE, 0xa6) | 2);
write32 (DEFAULT_RCBA + 0x2088, 0x00109000);
read32 (DEFAULT_RCBA + 0x20ac); // !!! = 0x00000000
write32 (DEFAULT_RCBA + 0x20ac, 0x40000000);
write32 (DEFAULT_RCBA + 0x100c, 0x01110000);
write8 (DEFAULT_RCBA + 0x2340, 0x1b);
read32 (DEFAULT_RCBA + 0x2314); // !!! = 0x0a080000
write32 (DEFAULT_RCBA + 0x2314, 0x0a280000);
read32 (DEFAULT_RCBA + 0x2310); // !!! = 0xc809605b
write32 (DEFAULT_RCBA + 0x2310, 0xa809605b);
write32 (DEFAULT_RCBA + 0x2324, 0x00854c74);
read8 (DEFAULT_RCBA + 0x0400); // !!! = 0x00
read32 (DEFAULT_RCBA + 0x2310); // !!! = 0xa809605b
write32 (DEFAULT_RCBA + 0x2310, 0xa809605b);
read32 (DEFAULT_RCBA + 0x2310); // !!! = 0xa809605b
write32 (DEFAULT_RCBA + 0x2310, 0xa809605b);
write_2338 (0xea007f62, 0x00590133);
write_2338 (0xec007f62, 0x00590133);
write_2338 (0xec007f64, 0x59555588);
write_2338 (0xea0040b9, 0x0001051c);
write_2338 (0xeb0040a1, 0x800084ff);
write_2338 (0xec0040a1, 0x800084ff);
write_2338 (0xea004001, 0x00008400);
write_2338 (0xeb004002, 0x40201758);
write_2338 (0xec004002, 0x40201758);
write_2338 (0xea004002, 0x00601758);
write_2338 (0xea0040a1, 0x810084ff);
write_2338 (0xeb0040b1, 0x0001c598);
write_2338 (0xec0040b1, 0x0001c598);
write_2338 (0xeb0040b6, 0x0001c598);
write_2338 (0xea0000a9, 0x80ff969f);
write_2338 (0xea0001a9, 0x80ff969f);
write_2338 (0xeb0040b2, 0x0001c396);
write_2338 (0xeb0040b3, 0x0001c396);
write_2338 (0xec0040b2, 0x0001c396);
write_2338 (0xea0001a9, 0x80ff94ff);
write_2338 (0xea000151, 0x0088037f);
write_2338 (0xea0000a9, 0x80ff94ff);
write_2338 (0xea000051, 0x0088037f);
write_2338 (0xea007f05, 0x00010642);
write_2338 (0xea0040b7, 0x0001c91c);
write_2338 (0xea0040b8, 0x0001c91c);
write_2338 (0xeb0040a1, 0x820084ff);
write_2338 (0xec0040a1, 0x820084ff);
write_2338 (0xea007f0a, 0xc2480000);
write_2338 (0xec00404d, 0x1ff177f);
write_2338 (0xec000084, 0x5a600000);
write_2338 (0xec000184, 0x5a600000);
write_2338 (0xec000284, 0x5a600000);
write_2338 (0xec000384, 0x5a600000);
write_2338 (0xec000094, 0x000f0501);
write_2338 (0xec000194, 0x000f0501);
write_2338 (0xec000294, 0x000f0501);
write_2338 (0xec000394, 0x000f0501);
write_2338 (0xec000096, 0x00000001);
write_2338 (0xec000196, 0x00000001);
write_2338 (0xec000296, 0x00000001);
write_2338 (0xec000396, 0x00000001);
write_2338 (0xec000001, 0x00008c08);
write_2338 (0xec000101, 0x00008c08);
write_2338 (0xec000201, 0x00008c08);
write_2338 (0xec000301, 0x00008c08);
write_2338 (0xec0040b5, 0x0001c518);
write_2338 (0xec000087, 0x06077597);
write_2338 (0xec000187, 0x06077597);
write_2338 (0xec000287, 0x06077597);
write_2338 (0xec000387, 0x06077597);
write_2338 (0xea000050, 0x00bb0157);
write_2338 (0xea000150, 0x00bb0157);
write_2338 (0xec007f60, 0x77777d77);
write_2338 (0xea00008d, 0x01320000);
write_2338 (0xea00018d, 0x01320000);
write_2338 (0xec0007b2, 0x04514b5e);
write_2338 (0xec00078c, 0x40000200);
write_2338 (0xec000780, 0x02000020);
init_dmi();
}

75
src/southbridge/intel/bd82x6x/early_usb.c
View File

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -22,35 +22,56 @@
#include <console/console.h>
#include <device/pci_ids.h>
#include <device/pci_def.h>
#include "northbridge/intel/sandybridge/sandybridge.h" /* For DEFAULT_RCBABASE. */
#include "pch.h"
#define PCH_EHCI1_TEMP_BAR0 0xe8000000
#define PCH_EHCI2_TEMP_BAR0 0xe8000400
/*
* Setup USB controller MMIO BAR to prevent the
* reference code from resetting the controller.
*
* The BAR will be re-assigned during device
* enumeration so these are only temporary.
*/
void enable_usb_bar(void)
void
early_usb_init (const struct southbridge_usb_port *portmap)
{
device_t usb0 = PCH_EHCI1_DEV;
device_t usb1 = PCH_EHCI2_DEV;
u32 cmd;
u32 reg32;
const u32 rcba_dump[8] = {
/* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050,
/* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630,
};
const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51, 0x2000094a, 0x2000035f };
int i;
/* Activate PMBAR. */
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
/* USB Controller 1 */
pci_write_config32(usb0, PCI_BASE_ADDRESS_0,
PCH_EHCI1_TEMP_BAR0);
cmd = pci_read_config32(usb0, PCI_COMMAND);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config32(usb0, PCI_COMMAND, cmd);
/* Unlock registers. */
outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c);
for (i = 0; i < 14; i++)
write32 (DEFAULT_RCBABASE + (0x3500 + 4 * i),
currents[portmap[i].current]);
for (i = 0; i < 10; i++)
write32 (DEFAULT_RCBABASE + (0x3538 + 4 * i), 0);
/* USB Controller 2 */
pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
PCH_EHCI2_TEMP_BAR0);
cmd = pci_read_config32(usb1, PCI_COMMAND);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config32(usb1, PCI_COMMAND, cmd);
for (i = 0; i < 8; i++)
write32 (DEFAULT_RCBABASE + (0x3560 + 4 * i), rcba_dump[i]);
for (i = 0; i < 8; i++)
write32 (DEFAULT_RCBABASE + (0x3580 + 4 * i), 0);
reg32 = 0;
for (i = 0; i < 14; i++)
if (!portmap[i].enabled)
reg32 |= (1 << i);
write32 (DEFAULT_RCBABASE + USBPDO, reg32);
reg32 = 0;
for (i = 0; i < 8; i++)
if (portmap[i].enabled && portmap[i].oc_pin >= 0)
reg32 |= (1 << (i + 8 * portmap[i].oc_pin));
write32 (DEFAULT_RCBABASE + USBOCM1, reg32);
reg32 = 0;
for (i = 8; i < 14; i++)
if (portmap[i].enabled && portmap[i].oc_pin >= 4)
reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4)));
write32 (DEFAULT_RCBABASE + USBOCM2, reg32);
for (i = 0; i < 22; i++)
write32 (DEFAULT_RCBABASE + (0x35a8 + 4 * i), 0);
pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
/* Relock registers. */
outw (0x0000, DEFAULT_PMBASE | 0x003c);
}

56
src/southbridge/intel/bd82x6x/early_usb_mrc.c Normal file
View File

@ -0,0 +1,56 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#include <arch/io.h>
#include <console/console.h>
#include <device/pci_ids.h>
#include <device/pci_def.h>
#include "pch.h"
#define PCH_EHCI1_TEMP_BAR0 0xe8000000
#define PCH_EHCI2_TEMP_BAR0 0xe8000400
/*
* Setup USB controller MMIO BAR to prevent the
* reference code from resetting the controller.
*
* The BAR will be re-assigned during device
* enumeration so these are only temporary.
*/
void enable_usb_bar(void)
{
device_t usb0 = PCH_EHCI1_DEV;
device_t usb1 = PCH_EHCI2_DEV;
u32 cmd;
/* USB Controller 1 */
pci_write_config32(usb0, PCI_BASE_ADDRESS_0,
PCH_EHCI1_TEMP_BAR0);
cmd = pci_read_config32(usb0, PCI_COMMAND);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config32(usb0, PCI_COMMAND, cmd);
/* USB Controller 2 */
pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
PCH_EHCI2_TEMP_BAR0);
cmd = pci_read_config32(usb1, PCI_COMMAND);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config32(usb1, PCI_COMMAND, cmd);
}

77
src/southbridge/intel/bd82x6x/early_usb_native.c
View File

@ -1,77 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#include <arch/io.h>
#include <console/console.h>
#include <device/pci_ids.h>
#include <device/pci_def.h>
#include "northbridge/intel/sandybridge/sandybridge.h" /* For DEFAULT_RCBABASE. */
#include "pch.h"
void
early_usb_init (const struct southbridge_usb_port *portmap)
{
u32 reg32;
const u32 rcba_dump[8] = {
/* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050,
/* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630,
};
const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51, 0x2000094a, 0x2000035f };
int i;
/* Activate PMBAR. */
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
/* Unlock registers. */
outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c);
for (i = 0; i < 14; i++)
write32 (DEFAULT_RCBABASE + (0x3500 + 4 * i),
currents[portmap[i].current]);
for (i = 0; i < 10; i++)
write32 (DEFAULT_RCBABASE + (0x3538 + 4 * i), 0);
for (i = 0; i < 8; i++)
write32 (DEFAULT_RCBABASE + (0x3560 + 4 * i), rcba_dump[i]);
for (i = 0; i < 8; i++)
write32 (DEFAULT_RCBABASE + (0x3580 + 4 * i), 0);
reg32 = 0;
for (i = 0; i < 14; i++)
if (!portmap[i].enabled)
reg32 |= (1 << i);
write32 (DEFAULT_RCBABASE + USBPDO, reg32);
reg32 = 0;
for (i = 0; i < 8; i++)
if (portmap[i].enabled && portmap[i].oc_pin >= 0)
reg32 |= (1 << (i + 8 * portmap[i].oc_pin));
write32 (DEFAULT_RCBABASE + USBOCM1, reg32);
reg32 = 0;
for (i = 8; i < 14; i++)
if (portmap[i].enabled && portmap[i].oc_pin >= 4)
reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4)));
write32 (DEFAULT_RCBABASE + USBOCM2, reg32);
for (i = 0; i < 22; i++)
write32 (DEFAULT_RCBABASE + (0x35a8 + 4 * i), 0);
pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
/* Relock registers. */
outw (0x0000, DEFAULT_PMBASE | 0x003c);
}

4
src/southbridge/intel/bd82x6x/usb_ehci.c
View File

@ -39,7 +39,7 @@ static void usb_ehci_init(struct device *dev)
printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
/* For others, done in MRC. */
#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) || IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE)
#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) || IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)
pci_write_config32(dev, 0x84, 0x930c8811);
pci_write_config32(dev, 0x88, 0x24000d30);
pci_write_config32(dev, 0xf4, 0x80408588);
@ -54,7 +54,7 @@ static void usb_ehci_init(struct device *dev)
pci_write_config32(dev, PCI_COMMAND, reg32);
/* For others, done in MRC. */
#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) || IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE)
#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) || IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)
struct resource *res;
u8 access_cntl;

2
util/autoport/sandybridge.go
View File

@ -124,7 +124,7 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
KconfigBool["VGA"] = true
KconfigBool["INTEL_EDID"] = true
KconfigBool["CPU_INTEL_SOCKET_RPGA989"] = true
KconfigBool["NORTHBRIDGE_INTEL_"+i.variant+"BRIDGE_NATIVE"] = true
KconfigBool["NORTHBRIDGE_INTEL_"+i.variant+"BRIDGE"] = true
KconfigBool["INTEL_INT15"] = true
KconfigBool["HAVE_ACPI_TABLES"] = true
KconfigBool["HAVE_ACPI_RESUME"] = true

4
util/board_status/to-wiki/towiki.sh
View File

@ -326,9 +326,9 @@ EOF
case $northbridge in
INTEL_HASWELL)
cpu_nice="Intel® 4th Gen (Haswell) Core i3/i5/i7";;
INTEL_IVYBRIDGE_NATIVE|INTEL_IVYBRIDGE|INTEL_FSP_IVYBRIDGE)
INTEL_IVYBRIDGE|INTEL_IVYBRIDGE_MRC|INTEL_FSP_IVYBRIDGE)
cpu_nice="Intel® 3rd Gen (Ivybridge) Core i3/i5/i7";;
INTEL_SANDYBRIDGE|INTEL_SANDYBRIDGE_NATIVE)
INTEL_SANDYBRIDGE|INTEL_SANDYBRIDGE_MRC)
cpu_nice="Intel® 2nd Gen (Sandybridge) Core i3/i5/i7";;
*)
cpu_nice="$northbridge";;