ec/google/chromeec: Define a sync IRQ if needed

Some boards are adding a second pin used for synchronization between
the EC and AP.  This is a direct connection between the EC and the SOC
that is intended to provide a lower latency interrupt signal for
sensors on the EC.

Currently the runtime EC interrupts assert an SCI before eventually
resulting in a Notify() on the MKBP device that the sensor driver users.
These extra layers add processing time and require additional EC
communication to determine the event source.

This interface was tested on a reworked Nocturne board with modified
EC and a modified kernel driver to ensure that the interrupt asserts
as expected and can be used by the kernel driver.

Change-Id: I49a11363ce82882e572bcb8923fd114ab6593fea
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/28758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/ec/google/chromeec/acpi/cros_ec.asl

@@ -22,6 +22,16 @@ Device (CREC)
 	Name (_PRW, Package () { EC_ENABLE_WAKE_PIN, 0x5 })
 #endif
 
+#ifdef EC_ENABLE_SYNC_IRQ
+	Name (_CRS, ResourceTemplate ()
+	{
+		Interrupt (ResourceConsumer, Edge, ActiveLow, Exclusive)
+		{
+			EC_SYNC_IRQ
+		}
+	})
+#endif
+
 #ifdef EC_ENABLE_MKBP_DEVICE
 	Device (CKSC)
 	{