baytrail: initialize graphics before MRC

The graphics device needs to have its resource contraints
initialized before running the reference code. Right now just
use a 256MiB aperture, 32MiB of stolen memory data, and 2MiB
GTT memory.

BUG=chrome-os-partner:22869
BRANCH=None
TEST=Built and booted. Noted amount of stolen memory matches
     configuration as well as BAR size within the graphics
     device.

Change-Id: I328bf858f288363187cf705d6340947393b5ff10
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170427
Reviewed-on: http://review.coreboot.org/4850
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/soc/intel/baytrail/baytrail/gfx.h

@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BAYTRAIL_GFX_H_
+#define _BAYTRAIL_GFX_H_
+
+/*
+ * PCI config registers.
+ */
+
+#define GGC		0x50
+# define GGC_VGA_DISABLE	(1 << 1)
+# define GGC_GTT_SIZE_MASK	(3 << 8)
+# define GGC_GTT_SIZE_0MB	(0 << 8)
+# define GGC_GTT_SIZE_1MB	(1 << 8)
+# define GGC_GTT_SIZE_2MB	(2 << 8)
+# define GGC_GSM_SIZE_MASK	(0x1f << 3)
+# define GGC_GSM_SIZE_0MB	(0 << 3)
+# define GGC_GSM_SIZE_32MB	(1 << 3)
+# define GGC_GSM_SIZE_64MB	(2 << 3)
+# define GGC_GSM_SIZE_128MB	(4 << 3)
+
+#define GSM_BASE	0x5c
+#define GTT_BASE	0x70
+
+#define MSAC		0x62
+#define  APERTURE_SIZE_MASK	(3 << 1)
+#define  APERTURE_SIZE_128MB	(0 << 1)
+#define  APERTURE_SIZE_256MB	(1 << 1)
+#define  APERTURE_SIZE_512MB	(3 << 1)
+
+#endif /* _BAYTRAIL_GFX_H_ */

src/soc/intel/baytrail/baytrail/romstage.h

@@ -36,6 +36,7 @@ void romstage_common(const struct romstage_params *params);
 void * asmlinkage romstage_main(unsigned long bist);
 void asmlinkage romstage_after_car(void);
 void raminit(struct mrc_params *mp, int prev_sleep_state);
+void gfx_init(void);
 
 #if CONFIG_ENABLE_BUILTIN_COM1
 void byt_config_com1_and_enable(void);

src/soc/intel/baytrail/romstage/Makefile.inc

@@ -2,3 +2,4 @@ cpu_incs += $(src)/soc/intel/baytrail/romstage/cache_as_ram.inc
 romstage-y += romstage.c
 romstage-y += raminit.c
 romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c
+romstage-y += gfx.c

src/soc/intel/baytrail/romstage/gfx.c

@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <baytrail/gfx.h>
+#include <baytrail/pci_devs.h>
+#include <baytrail/romstage.h>
+
+void gfx_init(void)
+{
+	uint32_t ggc;
+	uint8_t msac;
+	const unsigned int gfx_dev = PCI_DEV(0, GFX_DEV, GFX_FUNC);
+
+	/* The GFX device needs to set the aperture, gtt stolen size, and
+	 * graphics stolen memory stolen size before running MRC. For now
+	 * just hard code the defaults. Options can be added to the device
+	 * tree if needed. */
+
+	ggc = pci_read_config32(gfx_dev, GGC);
+	msac = pci_read_config8(gfx_dev, MSAC);
+
+	ggc &= ~(GGC_GTT_SIZE_MASK | GGC_GSM_SIZE_MASK);
+	ggc |= GGC_GTT_SIZE_2MB | GGC_GSM_SIZE_32MB;
+	/* Enable VGA decoding as well. */
+	ggc &= ~(GGC_VGA_DISABLE);
+
+	msac &= ~(APERTURE_SIZE_MASK);
+	msac |= APERTURE_SIZE_256MB;
+
+	pci_write_config32(gfx_dev, GGC, ggc);
+	pci_write_config8(gfx_dev, MSAC, msac);
+}

src/soc/intel/baytrail/romstage/romstage.c

@@ -89,6 +89,8 @@ void romstage_common(const struct romstage_params *params)
 
 	console_init();
 
+	gfx_init();
+
 	/* Initialize RAM */
 	raminit(params->mrc_params, 5);