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soc/amd/mendocino: Remove 2 unused PCIe functions 

Mendocino only has 4 PCIe lanes exposed, so there's no need for 6
PCIe functions to control them. These functions just show up as
leftover devicetree devices.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5b801d82f085d77706b8053a8fc9728101f155e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73853
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Martin Roth 2023-03-20 13:27:34 -06:00 committed by Felix Held
parent 8eacc74973
commit ed029a9c6c
1 changed files with 0 additions and 2 deletions
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2
src/soc/amd/mendocino/chipset_mendocino.cb
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@ -14,8 +14,6 @@ chip soc/amd/mendocino
device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end
device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end
device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end
device pci 02.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end
device pci 02.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end
device pci 08.0 on end # Dummy Host Bridge, do not disable
device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A