intel/fsp_baytrail: Add S3 suspend/resume Support
This adds S3 Suspend / Resume support to Intel's Bay Trail FSP It is based on the "src/soc/intel/baytrail/romstage/romstage.c" implementation. Change-Id: If0011068eb7290d1b764c5c4b12c17375fb69008 Signed-off-by: Mohan D'Costa <mohan@ndr.co.jp> Reviewed-on: http://review.coreboot.org/6937 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins)
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@ -63,6 +63,7 @@ config ENABLE_FSP_FAST_BOOT
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config ENABLE_MRC_CACHE
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bool
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default y if HAVE_ACPI_RESUME
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default n
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help
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Enabling this feature will cause MRC data to be cached in NV storage.
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@ -21,5 +21,8 @@
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Name(\_S0, Package(){0x0,0x0,0x0,0x0})
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// Name(\_S1, Package(){0x1,0x1,0x0,0x0})
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#if CONFIG_HAVE_ACPI_RESUME
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Name(\_S3, Package(){0x5,0x5,0x0,0x0})
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#endif
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Name(\_S4, Package(){0x6,0x6,0x0,0x0})
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Name(\_S5, Package(){0x7,0x7,0x0,0x0})
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@ -33,6 +33,7 @@ void report_platform_info(void);
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#include <fsptypes.h>
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void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr);
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uint32_t chipset_prev_sleep_state(uint32_t clear);
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#define NUM_ROMSTAGE_TS 4
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@ -28,7 +28,11 @@
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#include <baytrail/pci_devs.h>
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#include <drivers/intel/fsp/fsp_util.h>
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#include "../chip.h"
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#include <arch/io.h>
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#include <baytrail/reset.h>
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#include <baytrail/pmc.h>
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#include <baytrail/acpi.h>
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#include <baytrail/iomap.h>
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#ifdef __PRE_RAM__
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#include <baytrail/romstage.h>
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@ -307,18 +311,43 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams,
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FSP_INFO_HEADER *fsp_ptr)
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{
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FSP_INIT_RT_BUFFER *pFspRtBuffer = pFspInitParams->RtBufferPtr;
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uint32_t prev_sleep_state;
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/* Get previous sleep state but don't clear */
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prev_sleep_state = chipset_prev_sleep_state(0);
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printk(BIOS_INFO, "prev_sleep_state = S%d\n", prev_sleep_state);
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/* Initialize the UPD Data */
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GetUpdDefaultFromFsp (fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr);
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ConfigureDefaultUpdData(pFspRtBuffer->Common.UpdDataRgnPtr);
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pFspInitParams->NvsBufferPtr = NULL;
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pFspRtBuffer->Common.BootMode = BOOT_WITH_FULL_CONFIGURATION;
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#if IS_ENABLED(CONFIG_ENABLE_FSP_FAST_BOOT)
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#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
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/* Find the fastboot cache that was saved in the ROM */
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pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache();
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#endif
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if (prev_sleep_state == 3) {
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/* S3 resume */
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if ( pFspInitParams->NvsBufferPtr == NULL) {
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/* If waking from S3 and no cache then. */
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printk(BIOS_WARNING, "No MRC cache found in S3 resume path.\n");
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post_code(POST_RESUME_FAILURE);
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/* Clear Sleep Type */
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outl(inl(ACPI_BASE_ADDRESS + PM1_CNT) &
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~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
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/* Reboot */
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printk(BIOS_WARNING,"Rebooting..\n" );
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warm_reset();
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/* Should not reach here.. */
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die("Reboot System\n");
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}
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pFspRtBuffer->Common.BootMode = BOOT_ON_S3_RESUME;
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} else {
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/* Not S3 resume */
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pFspRtBuffer->Common.BootMode = BOOT_WITH_FULL_CONFIGURATION;
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}
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return;
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}
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@ -18,6 +18,7 @@
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*/
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#include <arch/cpu.h>
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#include <arch/acpi.h>
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#include <console/console.h>
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#include <cpu/intel/microcode.h>
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#include <cpu/x86/cr.h>
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@ -25,10 +26,12 @@
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#include <device/device.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <romstage_handoff.h>
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#include <stdlib.h>
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#include <baytrail/gpio.h>
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#include <baytrail/lpc.h>
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#include <baytrail/nvs.h>
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#include <baytrail/msr.h>
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#include <baytrail/pattrs.h>
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#include <baytrail/pci_devs.h>
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@ -123,6 +126,32 @@ static void fill_in_pattrs(void)
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}
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static inline void set_acpi_sleep_type(int val)
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{
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#if CONFIG_HAVE_ACPI_RESUME
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acpi_slp_type = val;
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#endif
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}
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static void s3_resume_prepare(void)
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{
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global_nvs_t *gnvs;
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struct romstage_handoff *romstage_handoff;
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gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
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romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO);
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if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) {
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if (gnvs != NULL) {
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memset(gnvs, 0, sizeof(global_nvs_t));
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}
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set_acpi_sleep_type(0);
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return;
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}
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set_acpi_sleep_type(3);
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}
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void baytrail_init_pre_device(void)
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{
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struct soc_gpio_config *config;
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@ -132,6 +161,9 @@ void baytrail_init_pre_device(void)
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/* Allow for SSE instructions to be executed. */
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write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT);
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/* Indicate S3 resume to rest of ramstage. */
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s3_resume_prepare();
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/* Get GPIO initial states from mainboard */
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config = mainboard_get_gpios();
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setup_soc_gpios(config);
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@ -24,6 +24,7 @@
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#include <arch/io.h>
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#include <arch/cbfs.h>
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#include <arch/stages.h>
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#include <arch/early_variables.h>
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#include <console/console.h>
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#include <cbmem.h>
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#include <cpu/x86/mtrr.h>
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@ -44,6 +45,51 @@
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#include <device/pci_def.h>
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#include <console/cbmem_console.h>
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/* Return 0, 3, 4 or 5 to indicate the previous sleep state. */
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uint32_t chipset_prev_sleep_state(uint32_t clear)
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{
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/* Default to S0. */
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uint32_t prev_sleep_state = 0;
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uint32_t pm1_sts;
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uint32_t pm1_cnt;
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uint32_t gen_pmcon1;
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/* Read Power State */
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pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
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pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
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gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
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printk(BIOS_DEBUG, "PM1_STS = 0x%x PM1_CNT = 0x%x GEN_PMCON1 = 0x%x\n",
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pm1_sts, pm1_cnt, gen_pmcon1);
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if (pm1_sts & WAK_STS) {
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switch ((pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
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#if CONFIG_HAVE_ACPI_RESUME
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case SLP_TYP_S3:
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prev_sleep_state = 3;
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break;
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#endif
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case SLP_TYP_S4:
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prev_sleep_state = 4;
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break;
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case SLP_TYP_S5:
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prev_sleep_state = 5;
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break;
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}
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/* If set Clear SLP_TYP. */
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if (clear == 1) {
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outl(pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
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}
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}
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if (gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) {
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prev_sleep_state = 5;
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}
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return prev_sleep_state;
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}
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static void program_base_addresses(void)
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{
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uint32_t reg;
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@ -174,6 +220,8 @@ void * asmlinkage main(FSP_INFO_HEADER *fsp_info_header)
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void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
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int cbmem_was_initted;
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void *cbmem_hob_ptr;
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uint32_t prev_sleep_state;
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struct romstage_handoff *handoff;
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#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
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tsc_t after_initram_time = rdtsc();
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@ -193,6 +241,10 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
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printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status);
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/* Get previous sleep state again and clear */
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prev_sleep_state = chipset_prev_sleep_state(1);
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printk(BIOS_DEBUG, "%s: prev_sleep_state = S%d\n", __func__, prev_sleep_state);
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report_platform_info();
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#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
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late_mainboard_romstage_entry();
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post_code(0x4c);
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quick_ram_check();
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post_code(0x4d);
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/* if S3 resume skip ram check */
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if (prev_sleep_state != 3) {
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quick_ram_check();
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post_code(0x4d);
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}
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cbmem_was_initted = !cbmem_recovery(0);
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cbmem_was_initted = !cbmem_recovery(prev_sleep_state == 3);
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/* Save the HOB pointer in CBMEM to be used in ramstage*/
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cbmem_hob_ptr = cbmem_add (CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr));
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*(u32*)cbmem_hob_ptr = (u32)hob_list_ptr;
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post_code(0x4e);
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handoff = romstage_handoff_find_or_add();
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if (handoff != NULL)
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handoff->s3_resume = (prev_sleep_state == 3);
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else
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printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
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#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
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timestamp_init(base_time);
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timestamp_reinit();
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