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soc/intel/skylake: move i2c voltage config to own variable 

In preparation of merging the lpss i2c config structures on
apollolake and skylake move the i2c voltage variable to its
own field. It makes refactoring things easier, and then there's
no reason for a separate SoC specific i2c config structure.

BUG=chrome-os-partner:58889

Change-Id: Ibcc3cba9bac3b5779351b673bc0cc7671d127f24
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17347
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Aaron Durbin 2016-11-09 17:04:15 -06:00
parent ce21151a1c
commit ed14a4e0df
8 changed files with 13 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/chell/devicetree.cb
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@ -163,7 +163,7 @@ chip soc/intel/skylake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port
register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # SD
register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{

10
src/mainboard/google/eve/devicetree.cb
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@ -160,11 +160,11 @@ chip soc/intel/skylake
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
register "i2c[0].voltage" = "I2C_VOLTAGE_3V3" # Touchscreen
register "i2c[1].voltage" = "I2C_VOLTAGE_3V3" # TPM
register "i2c[2].voltage" = "I2C_VOLTAGE_1V8" # Touchpad
register "i2c[3].voltage" = "I2C_VOLTAGE_1V8" # Display
register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # Audio
register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # Touchscreen
register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM
register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" # Touchpad
register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" # Display
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # Audio
# Enable I2C1 bus early for TPM access
register "i2c[1].early_init" = "1"

2
src/mainboard/google/glados/devicetree.cb
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@ -163,7 +163,7 @@ chip soc/intel/skylake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port 1
register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port 2
register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{

2
src/mainboard/google/lars/devicetree.cb
View File

@ -160,7 +160,7 @@ chip soc/intel/skylake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card)
register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board)
register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{ \

2
src/mainboard/intel/kunimitsu/devicetree.cb
View File

@ -164,7 +164,7 @@ chip soc/intel/skylake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card)
register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board)
register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{ \

2
src/soc/intel/skylake/chip.c
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@ -163,7 +163,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
params->SkipMpInit = config->FspSkipMpInit;
for (i = 0; i < ARRAY_SIZE(config->i2c); i++)
params->SerialIoI2cVoltage[i] = config->i2c[i].voltage;
params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];
/*
* To disable Heci, the Psf needs to be left unlocked

4
src/soc/intel/skylake/chip.h
View File

@ -40,8 +40,6 @@ enum skylake_i2c_voltage {
};
struct skylake_i2c_config {
/* Bus voltage level, default is 3.3V */
enum skylake_i2c_voltage voltage;
/* Bus speed in Hz, default is I2C_SPEED_FAST (400 KHz) */
enum i2c_speed speed;
/* Bus should be enabled prior to ramstage with temporary base */
@ -201,6 +199,8 @@ struct soc_intel_skylake_config {
u8 SerialIoDevMode[PchSerialIoIndexMax];
/* I2C */
/* Bus voltage level, default is 3.3V */
enum skylake_i2c_voltage i2c_voltage[SKYLAKE_I2C_DEV_MAX];
struct skylake_i2c_config i2c[SKYLAKE_I2C_DEV_MAX];
/* Camera */

2
src/soc/intel/skylake/chip_fsp20.c
View File

@ -203,7 +203,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->CpuConfig.Bits.SkipMpInit = config->FspSkipMpInit;
for (i = 0; i < ARRAY_SIZE(config->i2c); i++)
params->SerialIoI2cVoltage[i] = config->i2c[i].voltage;
params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];
for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)
fill_vr_domain_config(params, i, &config->domain_vr_config[i]);