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Replace clear_memory with memset. 

Replace set_init_ram_access with the call to set_var_mtrr.
Remove unused #include statments.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson 2010-03-11 21:34:27 +00:00
parent bc259d09d3
commit ed15220b87
19 changed files with 11 additions and 60 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
src/cpu/amd/car/clear_init_ram.c
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@ -1,23 +0,0 @@
/* by yhlu 6.2005 */
/* be warned, this file will be used core 0/node 0 only */
static void __attribute__((noinline)) clear_init_ram(void)
{
// gcc 3.4.5 will inline the copy_and_run and clear_init_ram in post_cache_as_ram
// will reuse %edi as 0 from clear_memory for copy_and_run part, actually it is increased already
// so noline clear_init_ram
#if CONFIG_HAVE_ACPI_RESUME == 1
/* clear only coreboot used region of memory. Note: this may break ECC enabled boards */
clear_memory( CONFIG_RAMBASE, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE);
#else
clear_memory(0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE));
#endif
}
/* be warned, this file will be used by core other than core 0/node 0 or core0/node0 when cpu_reset*/
static void set_init_ram_access(void)
{
set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
}

12
src/cpu/amd/car/post_cache_as_ram.c
View File

@ -3,8 +3,6 @@
*/
#include "cpu/amd/car/disable_cache_as_ram.c"
#include "cpu/amd/car/clear_init_ram.c"
static inline void print_debug_pcar(const char *strval, uint32_t val)
{
printk_debug("%s%08x\r\n", strval, val);
@ -64,7 +62,8 @@ static void post_cache_as_ram(void)
#error "You need to set CONFIG_RAMTOP greater than 1M"
#endif
set_init_ram_access(); /* So we can access RAM from [1M, CONFIG_RAMTOP) */
/* So we can access RAM from [1M, CONFIG_RAMTOP) */
set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x8000, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x7c00);
print_debug("Copying data from cache to RAM -- switching to use RAM as stack... ");
@ -94,7 +93,12 @@ static void post_cache_as_ram(void)
disable_cache_as_ram_bsp();
print_debug("Clearing initial memory region: ");
clear_init_ram(); //except the range from [(CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE, (CONFIG_RAMTOP))
#if CONFIG_HAVE_ACPI_RESUME == 1
/* clear only coreboot used region of memory. Note: this may break ECC enabled boards */
memset((void*) CONFIG_RAMBASE, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE, 0);
#else
memset((void*)0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE), 0);
#endif
print_debug("Done\r\n");
// dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);

2
src/cpu/amd/model_10xxx/init_cpus.c
View File

@ -421,7 +421,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
*/
//wait_till_sysinfo_in_ram();
set_init_ram_access();
set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
STOP_CAR_AND_CPU();
printk_debug("\nAP %02x should be halted but you are reading this....\n", apicid);

1
src/cpu/amd/model_10xxx/model_10xxx_init.c
View File

@ -34,7 +34,6 @@
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/mem.h>
#include <cpu/amd/quadcore.h>
#include <cpu/amd/model_10xxx_msr.h>

2
src/cpu/amd/model_fxx/init_cpus.c
View File

@ -317,7 +317,7 @@ static unsigned init_cpus(unsigned cpu_init_detectedx)
print_initcpu8("while waiting for BSP signal to STOP, timeout in ap ", apicid);
}
lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu
set_init_ram_access();
set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
#if CONFIG_MEM_TRAIN_SEQ == 1
train_ram_on_node(id.nodeid, id.coreid, sysinfo,
(unsigned) STOP_CAR_AND_CPU);

3
src/cpu/amd/model_fxx/model_fxx_init.c
View File

@ -24,7 +24,6 @@
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/mem.h>
#include <cpu/amd/dualcore.h>
@ -238,7 +237,7 @@ static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_sta
/* clear memory 2M (limitk - basek) */
addr = (void *)(((uint32_t)addr) | ((basek & 0x7ff) << 10));
clear_memory(addr, size);
memset(addr, size, 0);
}
static void init_ecc_memory(unsigned node_id)

16
src/include/cpu/x86/mem.h
View File

@ -1,16 +0,0 @@
#ifndef CPU_X86_MEM_H
#define CPU_X86_MEM_H
/* Optimized generic x86 assembly for clearing memory */
static inline void clear_memory(void *addr, unsigned long size)
{
asm volatile(
"cld \n\t"
"rep; stosl\n\t"
: /* No outputs */
: "a" (0), "D" (addr), "c" (size>>2)
);
}
#endif /* CPU_X86_MEM_H */

1
src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
View File

@ -130,7 +130,6 @@ static int spd_read_byte(u32 device, u32 address)
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "northbridge/amd/amdht/ht_wrapper.c"
#include "include/cpu/x86/mem.h"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/raminit_amdmct.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"

1
src/mainboard/msi/ms9652_fam10/romstage.c
View File

@ -110,7 +110,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "northbridge/amd/amdht/ht_wrapper.c"
#include "include/cpu/x86/mem.h"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/raminit_amdmct.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"

1
src/mainboard/supermicro/h8dmr_fam10/romstage.c
View File

@ -108,7 +108,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "northbridge/amd/amdht/ht_wrapper.c"
#include "include/cpu/x86/mem.h"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/raminit_amdmct.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"

1
src/mainboard/supermicro/h8qme_fam10/romstage.c
View File

@ -108,7 +108,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "northbridge/amd/amdht/ht_wrapper.c"
#include "include/cpu/x86/mem.h"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/raminit_amdmct.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"

1
src/mainboard/tyan/s2912_fam10/romstage.c
View File

@ -110,7 +110,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "northbridge/amd/amdht/ht_wrapper.c"
#include "include/cpu/x86/mem.h"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/raminit_amdmct.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"

1
src/northbridge/amd/amdk8/raminit.c
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@ -4,7 +4,6 @@
2005.02 yhlu add E0 memory hole support
*/
#include <cpu/x86/mem.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
#include <stdlib.h>

1
src/northbridge/amd/amdk8/raminit_f.c
View File

@ -20,7 +20,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cpu/x86/mem.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/tsc.h>

1
src/northbridge/intel/e7520/raminit.c
View File

@ -18,7 +18,6 @@
*
*/
#include <cpu/x86/mem.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <stdlib.h>

1
src/northbridge/intel/e7525/raminit.c
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@ -18,7 +18,6 @@
*
*/
#include <cpu/x86/mem.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <stdlib.h>

1
src/northbridge/intel/i3100/raminit.c
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@ -19,7 +19,6 @@
*
*/
#include <cpu/x86/mem.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <stdlib.h>

1
src/northbridge/intel/i3100/raminit_ep80579.c
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@ -19,7 +19,6 @@
*
*/
#include <cpu/x86/mem.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include "raminit_ep80579.h"

1
src/northbridge/intel/i945/raminit.c
View File

@ -17,7 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cpu/x86/mem.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <spd.h>