From ed1c03a138ccfb4d1939f15fbe97ab0b8f7e4015 Mon Sep 17 00:00:00 2001 From: Sukumar Ghorai Date: Thu, 28 Sep 2023 23:44:30 -0700 Subject: [PATCH] soc/intel: separate slp-s0 residency counter frequency in LPIT table MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Intel platforms use Low Power Idle Table (LPIT) to enumerate platform Low Power Idle states. There are two types of low power residencies a) CPU PKG C10 - read via MSR (Function fixed hardware interface) b) Platform Controller Hub (PCH) SLP_S0 - read via memory mapped IO Ref. https://www.uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_Idle.pdf, section 2.2.1: value of 0 indicates that counter runs at TSC frequency. Ref. Intel 64 and IA-32 Architectures Software Developer’s Manual (Vol 4) MSR 0x632: PC10 residency counter is at same frequency as the TSC. Whereas slp_s0 residency counter running in different frequency. BUG=b:300440936 TEST=check kernel cpuidle sysfs are created after kernel boot cat /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us cat /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us Change-Id: Ibde764551a21b9aecb1c269948f4823548294711 Signed-off-by: Sukumar Ghorai Reviewed-on: https://review.coreboot.org/c/coreboot/+/78177 Tested-by: build bot (Jenkins) Reviewed-by: Kapil Porwal Reviewed-by: Subrata Banik --- src/include/acpi/acpi.h | 3 ++- src/soc/intel/common/block/acpi/lpit.c | 4 ++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 141e4d3ad8..eae84a8071 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -453,7 +453,8 @@ typedef struct acpi_lpi_desc_hdr { uint16_t reserved; } __packed acpi_lpi_desc_hdr_t; -#define ACPI_LPIT_CTR_FREQ_TSC 0 +#define ACPI_LPIT_CTR_FREQ_TSC 0 +#define ACPI_LPIT_SLP_S0_FREQ 0 /* LPIT: Native C-state instruction based LPI structure */ typedef struct acpi_lpi_desc_ncst { diff --git a/src/soc/intel/common/block/acpi/lpit.c b/src/soc/intel/common/block/acpi/lpit.c index 38a402f13d..de1e71dc24 100644 --- a/src/soc/intel/common/block/acpi/lpit.c +++ b/src/soc/intel/common/block/acpi/lpit.c @@ -50,13 +50,13 @@ unsigned long acpi_fill_lpit(unsigned long current) sys_counter->entry_trigger.space_id = ACPI_ADDRESS_SPACE_FIXED; sys_counter->entry_trigger.access_size = ACPI_ACCESS_SIZE_UNDEFINED; - /* Slp_S0 residency counter */ + /* slp_s0 residency counter */ sys_counter->residency_counter.addrl = PCH_PWRM_BASE_ADDRESS + SLP_S0_RES; sys_counter->residency_counter.bit_offset = 0; sys_counter->residency_counter.bit_width = 32; sys_counter->residency_counter.space_id = ACPI_ADDRESS_SPACE_MEMORY; sys_counter->residency_counter.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - sys_counter->counter_frequency = ACPI_LPIT_CTR_FREQ_TSC; + sys_counter->counter_frequency = ACPI_LPIT_SLP_S0_FREQ; /* Min. residency and worst-case latency (from FSP and vendor dumps) */ sys_counter->min_residency = 30000; /* break-even: 30 ms */