Add compile-time defaults to some K8 CMOS options in case they're absent in CMOS

This affects the CMOS options iommu, ECC_memory, max_mem_clock,
hw_scrubber, interleave_chip_selects.
If they're absent in cmos.layout, a Kconfig value is used if it exists,
or a hardcoded default otherwise.

[Patrick: I changed the ramstage CMOS handling a bit, and dropped the
reliance of hw_scrubber on ECC RAM, as it has nothing to do with it -
it's the cache that's being scrubbed here.]

Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Josef Kellermann 2011-02-24 14:35:42 +00:00 committed by Patrick Georgi
parent 855224bb28
commit ed1d116e62
5 changed files with 45 additions and 10 deletions

View File

@ -14,6 +14,10 @@ config SET_FIDVID
default n default n
default y if K8_REV_F_SUPPORT default y if K8_REV_F_SUPPORT
config HW_SCRUBBER
bool
default n
if SET_FIDVID if SET_FIDVID
config SET_FIDVID_DEBUG config SET_FIDVID_DEBUG
bool bool

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@ -264,7 +264,10 @@ static void init_ecc_memory(unsigned node_id)
/* See if we scrubbing should be enabled */ /* See if we scrubbing should be enabled */
enable_scrubbing = 1; enable_scrubbing = 1;
get_option(&enable_scrubbing, "hw_scrubber"); if( get_option(&enable_scrubbing, "hw_scrubber") < 0 )
{
enable_scrubbing = CONFIG_HW_SCRUBBER;
}
/* Enable cache scrubbing at the lowest possible rate */ /* Enable cache scrubbing at the lowest possible rate */
if (enable_scrubbing) { if (enable_scrubbing) {

View File

@ -83,6 +83,10 @@ endif #DIMM_DDR2
endif #K8_REV_F_SUPPORT endif #K8_REV_F_SUPPORT
config IOMMU
bool
default y
endif #NORTHBRIDGE_AMD_K8 endif #NORTHBRIDGE_AMD_K8
source src/northbridge/amd/amdk8/root_complex/Kconfig source src/northbridge/amd/amdk8/root_complex/Kconfig

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@ -48,7 +48,10 @@ static void mcf3_read_resources(device_t dev)
} }
iommu = 1; iommu = 1;
get_option(&iommu, "iommu"); if( get_option(&iommu, "iommu") < 0 )
{
iommu = CONFIG_IOMMU;
}
if (iommu) { if (iommu) {
/* Add a GART aperture resource */ /* Add a GART aperture resource */

View File

@ -1107,6 +1107,15 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl,
/* See if all of the memory chip selects are the same size /* See if all of the memory chip selects are the same size
* and if so count them. * and if so count them.
*/ */
#if defined(CMOS_VSTART_interleave_chip_selects)
if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) == 0)
return 0;
#else
#if !defined(CONFIG_INTERLEAVE_CHIP_SELECTS) || (CONFIG_INTERLEAVE_CHIP_SELECTS == 0)
return 0;
#endif
#endif
chip_selects = 0; chip_selects = 0;
common_size = 0; common_size = 0;
common_cs_mode = 0xff; common_cs_mode = 0xff;
@ -1279,15 +1288,10 @@ static void order_dimms(const struct mem_controller *ctrl,
{ {
unsigned long tom_k, base_k; unsigned long tom_k, base_k;
if (read_option(CMOS_VSTART_interleave_chip_selects,
CMOS_VLEN_interleave_chip_selects, 1) != 0) {
tom_k = interleave_chip_selects(ctrl, meminfo->is_Width128); tom_k = interleave_chip_selects(ctrl, meminfo->is_Width128);
} else {
printk(BIOS_DEBUG, "Interleaving disabled\n");
tom_k = 0;
}
if (!tom_k) { if (!tom_k) {
printk(BIOS_DEBUG, "Interleaving disabled\n");
tom_k = order_chip_selects(ctrl); tom_k = order_chip_selects(ctrl);
} }
@ -1801,7 +1805,17 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
bios_cycle_time = min_cycle_times[ bios_cycle_time = min_cycle_times[
read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)]; #ifdef CMOS_VSTART_max_mem_clock
read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)
#else
#if defined(CONFIG_MAX_MEM_CLOCK)
CONFIG_MAX_MEM_CLOCK
#else
0 // use DDR400 as default
#endif
#endif
];
if (bios_cycle_time > min_cycle_time) { if (bios_cycle_time > min_cycle_time) {
min_cycle_time = bios_cycle_time; min_cycle_time = bios_cycle_time;
} }
@ -2360,14 +2374,21 @@ static void set_ecc(const struct mem_controller *ctrl,
if (nbcap & NBCAP_ECC) { if (nbcap & NBCAP_ECC) {
dcl |= DCL_DimmEccEn; dcl |= DCL_DimmEccEn;
} }
#ifdef CMOS_VSTART_ECC_memory
if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) { if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
dcl &= ~DCL_DimmEccEn; dcl &= ~DCL_DimmEccEn;
} }
#else // CMOS_VSTART_ECC_memory not defined
#if defined(CONFIG_ECC_MEMORY) && (CONFIG_ECC_MEMORY == 0)
dcl &= ~DCL_DimmEccEn;
#endif
#endif
pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
meminfo->is_ecc = 1; meminfo->is_ecc = 1;
if (!(dcl & DCL_DimmEccEn)) { if (!(dcl & DCL_DimmEccEn)) {
meminfo->is_ecc = 0; meminfo->is_ecc = 0;
printk(BIOS_DEBUG, "set_ecc: ECC disabled\n");
return; // already disabled the ECC, so don't need to read SPD any more return; // already disabled the ECC, so don't need to read SPD any more
} }