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mb/intel/adlrvp: Add 5G WWAN ACPI support for adlrvp_rpl_ext_ec 

Add FM350GL 5G WWAN support using drivers/wwan/fm and additional PM
features from RTD3.

TEST=Check SSDT table to see if the PXSX device and PowerResource RTD3
are generated under the root port.

BRANCH=firmware-brya-14505.B

Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: I74434d833086f639927d8369f8a6e3af31dd99e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64648
Reviewed-by: Jeremy Compostella <jeremy.compostella@intel.corp-partner.google.com>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Cliff Huang 2022-05-24 13:46:27 -07:00 committed by Felix Held
parent 67d4ed82a9
commit ed29baddfb
2 changed files with 28 additions and 0 deletions
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1
src/mainboard/intel/adlrvp/Kconfig
View File

@ -39,6 +39,7 @@ config BOARD_INTEL_ADLRVP_RPL_EXT_EC
select INTEL_LPSS_UART_FOR_CONSOLE
select SOC_INTEL_ALDERLAKE_PCH_P
select GEN3_EXTERNAL_CLOCK_BUFFER
select DRIVERS_WWAN_FM350GL
config BOARD_INTEL_ADLRVP_P_MCHP
select BOARD_INTEL_ADLRVP_COMMON

27
src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb
View File

@ -57,5 +57,32 @@ chip soc/intel/alderlake
end
end
end
device ref pcie_rp6 on
# Enable WWAN PCIE 6 using clk 5
register "pch_pcie_rp[PCH_RP(6)]" = "{
.clk_src = 5,
.clk_req = 5,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C5)"
register "reset_off_delay_ms" = "20"
register "srcclk_pin" = "5"
register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
register "skip_on_off_support" = "true"
device generic 0 alias rp6_rtd3 on
end
end
chip drivers/wwan/fm
register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F15)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F14)"
register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C5)"
register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
register "add_acpi_dma_property" = "true"
use rp6_rtd3 as rtd3dev
device generic 0 on
end
end
end
end
end