sb/intel/common/smi*: Use new PMBASE API
Use new PMBASE API functions in common SMI handler. Change-Id: I4c64233ecdb8c1e28b319d84149f34bc8f1e4b97 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Patrick Rudolph
Patrick Rudolph
parent
853bb4dc11
commit
ed3242e338
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@ -23,16 +23,15 @@
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#include <cpu/x86/cache.h>
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#include <cpu/x86/smm.h>
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#include <cpu/intel/smm/gen1/smi.h>
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#include <southbridge/intel/common/pmbase.h>
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#include "pmutil.h"
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#define DEBUG_PERIODIC_SMIS 0
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static u16 pmbase;
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u16 get_pmbase(void)
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{
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return pmbase;
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return lpc_get_pmbase();
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}
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void southbridge_smm_init(void)
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@ -48,12 +47,9 @@ void southbridge_smm_init(void)
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printk(BIOS_DEBUG, "Initializing southbridge SMI...");
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pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
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D31F0_PMBASE) & 0xff80;
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printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", lpc_get_pmbase());
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printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
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smi_en = inl(pmbase + SMI_EN);
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smi_en = read_pmbase32(SMI_EN);
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if (smi_en & APMC_EN) {
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printk(BIOS_INFO, "SMI# handler already enabled?\n");
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return;
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@ -67,14 +63,14 @@ void southbridge_smm_init(void)
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dump_tco_status(reset_tco_status());
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/* Disable GPE0 PME_B0 */
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gpe0_en = inl(pmbase + GPE0_EN);
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gpe0_en = read_pmbase32(GPE0_EN);
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gpe0_en &= ~PME_B0_EN;
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outl(gpe0_en, pmbase + GPE0_EN);
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write_pmbase32(GPE0_EN, gpe0_en);
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pm1_en = 0;
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pm1_en |= PWRBTN_EN;
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pm1_en |= GBL_EN;
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outw(pm1_en, pmbase + PM1_EN);
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write_pmbase16(PM1_EN, pm1_en);
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/* Enable SMI generation:
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* - on TCO events
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@ -106,7 +102,7 @@ void southbridge_smm_init(void)
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/* The following need to be on for SMIs to happen */
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smi_en |= EOS | GBL_SMI_EN;
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outl(smi_en, pmbase + SMI_EN);
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write_pmbase32(SMI_EN, smi_en);
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}
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void southbridge_trigger_smi(void)
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@ -25,21 +25,21 @@
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#include <elog.h>
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#include <halt.h>
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#include <pc80/mc146818rtc.h>
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#include <southbridge/intel/common/pmbase.h>
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#include "pmutil.h"
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static int smm_initialized = 0;
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static u16 pmbase;
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u16 get_pmbase(void)
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{
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return pmbase;
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return lpc_get_pmbase();
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}
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/* Defined in <cpu/x86/smm.h> which is used outside of common code*/
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u16 smm_get_pmbase(void)
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{
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return get_pmbase();
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return lpc_get_pmbase();
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}
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void gpi_route_interrupt(u8 gpi, u8 mode)
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@ -67,11 +67,7 @@ void gpi_route_interrupt(u8 gpi, u8 mode)
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*/
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void southbridge_smi_set_eos(void)
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{
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u8 reg8;
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reg8 = inb(pmbase + SMI_EN);
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reg8 |= EOS;
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outb(reg8, pmbase + SMI_EN);
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write_pmbase8(SMI_EN, read_pmbase8(SMI_EN) | EOS);
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}
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static void busmaster_disable_on_bus(int bus)
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@ -134,12 +130,10 @@ static void southbridge_smi_sleep(void)
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outb(tmp72, 0x72);
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/* First, disable further SMIs */
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reg8 = inb(pmbase + SMI_EN);
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reg8 &= ~SLP_SMI_EN;
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outb(reg8, pmbase + SMI_EN);
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write_pmbase8(SMI_EN, read_pmbase8(SMI_EN) & ~SLP_SMI_EN);
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/* Figure out SLP_TYP */
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reg32 = inl(pmbase + PM1_CNT);
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reg32 = read_pmbase32(PM1_CNT);
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printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
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slp_typ = acpi_sleep_from_pm1(reg32);
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@ -179,7 +173,7 @@ static void southbridge_smi_sleep(void)
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case ACPI_S5:
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printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
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outl(0, pmbase + GPE0_EN);
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write_pmbase32(GPE0_EN, 0);
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/* Always set the flag in case CMOS was changed on runtime. For
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* "KEEP", switch to "OFF" - KEEP is software emulated
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@ -202,7 +196,7 @@ static void southbridge_smi_sleep(void)
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* event again. We need to set BIT13 (SLP_EN) though to make the
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* sleep happen.
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*/
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outl(reg32 | SLP_EN, pmbase + PM1_CNT);
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write_pmbase32(PM1_CNT, reg32 | SLP_EN);
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/* Make sure to stop executing code here for S3/S4/S5 */
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if (slp_typ >= ACPI_S3)
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@ -212,11 +206,11 @@ static void southbridge_smi_sleep(void)
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* the line above. However, if we entered sleep state S1 and wake
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* up again, we will continue to execute code in this function.
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*/
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reg32 = inl(pmbase + PM1_CNT);
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reg32 = read_pmbase32(PM1_CNT);
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if (reg32 & SCI_EN) {
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/* The OS is not an ACPI OS, so we set the state to S0 */
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reg32 &= ~(SLP_EN | SLP_TYP);
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outl(reg32, pmbase + PM1_CNT);
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write_pmbase32(PM1_CNT, reg32);
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}
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}
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@ -283,7 +277,6 @@ static int mainboard_finalized = 0;
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static void southbridge_smi_apmc(void)
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{
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u32 pmctrl;
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u8 reg8;
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/* Emulate B2 register as the FADT / Linux expects it */
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@ -305,15 +298,11 @@ static void southbridge_smi_apmc(void)
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printk(BIOS_DEBUG, "P-state control\n");
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break;
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case APM_CNT_ACPI_DISABLE:
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pmctrl = inl(pmbase + PM1_CNT);
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pmctrl &= ~SCI_EN;
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outl(pmctrl, pmbase + PM1_CNT);
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write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) & ~SCI_EN);
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printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
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break;
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case APM_CNT_ACPI_ENABLE:
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pmctrl = inl(pmbase + PM1_CNT);
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pmctrl |= SCI_EN;
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outl(pmctrl, pmbase + PM1_CNT);
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write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | SCI_EN);
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printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
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break;
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case APM_CNT_GNVS_UPDATE:
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@ -360,7 +349,7 @@ static void southbridge_smi_pm1(void)
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#if IS_ENABLED(CONFIG_ELOG_GSMI)
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elog_add_event(ELOG_TYPE_POWER_BUTTON);
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#endif
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outl(reg32, pmbase + PM1_CNT);
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write_pmbase32(PM1_CNT, reg32);
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}
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}
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@ -375,24 +364,23 @@ static void southbridge_smi_gpe0(void)
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static void southbridge_smi_gpi(void)
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{
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u16 reg16;
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reg16 = inw(pmbase + ALT_GP_SMI_STS);
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outw(reg16, pmbase + ALT_GP_SMI_STS);
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reg16 &= inw(pmbase + ALT_GP_SMI_EN);
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reg16 = reset_alt_gp_smi_status();
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reg16 &= read_pmbase16(ALT_GP_SMI_EN);
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mainboard_smi_gpi(reg16);
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if (reg16)
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printk(BIOS_DEBUG, "GPI (mask %04x)\n", reg16);
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outw(reg16, pmbase + ALT_GP_SMI_STS);
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write_pmbase16(ALT_GP_SMI_STS, reg16);
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}
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static void southbridge_smi_mc(void)
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{
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u32 reg32;
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reg32 = inl(pmbase + SMI_EN);
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reg32 = read_pmbase32(SMI_EN);
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/* Are periodic SMIs enabled? */
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if ((reg32 & MCSMI_EN) == 0)
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@ -445,7 +433,7 @@ static void southbridge_smi_periodic(void)
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{
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u32 reg32;
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reg32 = inl(pmbase + SMI_EN);
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reg32 = read_pmbase32(SMI_EN);
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/* Are periodic SMIs enabled? */
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if ((reg32 & PERIODIC_EN) == 0)
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@ -501,9 +489,6 @@ void southbridge_smi_handler(void)
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int i, dump = 0;
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u32 smi_sts;
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/* Update global variable pmbase */
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pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
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/* We need to clear the SMI status registers, or we won't see what's
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* happening in the following calls.
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*/
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