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soc/amd/common/block/i2c/i23c_pad_ctrl: only configure mode and voltage 

The fch_i23c_pad_init implementation was written without looking at any
reference code and turned out to not work properly on hardware. Before
this function writes to the MISC_I23C_PAD_CTRL registers, the value read
back is 0x3000003c which results in the I2C bus communication to work
while the 0x300003fc the code writes to the register breaks the I2C
communication. Removing the code that sets bits 6..9 fixes the I2C bus
communication.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ie6758b3d13c59b20ce810225fca8a365713b7a2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63234
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2022-03-31 01:37:57 +02:00
parent e0c738c3df
commit ed32977a39
1 changed files with 0 additions and 7 deletions
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7
src/soc/amd/common/block/i2c/i23c_pad_ctrl.c
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@ -44,12 +44,5 @@ void fch_i23c_pad_init(unsigned int bus,
break;
}
pad_ctrl &= ~I23C_PAD_CTRL_FALLSLEW_SEL_MASK;
pad_ctrl |= speed == I2C_SPEED_STANDARD ?
I23C_PAD_CTRL_FALLSLEW_SEL_STD : I23C_PAD_CTRL_FALLSLEW_SEL_LOW;
pad_ctrl &= ~I23C_PAD_CTRL_SLEW_N_MASK;
pad_ctrl |= I23C_PAD_CTRL_SLEW_N_FAST;
misc_write32(MISC_I23C_PAD_CTRL(bus), pad_ctrl);
}