soc/intel/xeon_sp/cpx: display UPDs and CPX-SP specific HOBs
Support display of CPX-SP specific HOBs (when CONFIG_DISPLAY_HOBS is selected, and UPD parameters (when CONFIG_DISPLAY_UPD_DATA is selected). Such display is used for FSP debugging purpose. It adds small amount of boot time. Some UPD display log excerpts: UPD values for SiliconInit: 0x04: BifurcationPcie0 0x03: BifurcationPcie1 Some HOB display log excerpts: === FSP HOBs === 0x758df000: hob_list_ptr 0x758df000, 0x00000038 bytes: HOB_TYPE_HANDOFF 0x758df038, 0x00000028 bytes: HOB_TYPE_MEMORY_POOL Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: I42dd519103cc604d4cfee858f4774bd73c979e77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41348 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jonathan Zhang
Patrick Georgi
parent
eba0433b17
commit
ed624c7158
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@ -9,7 +9,11 @@ subdirs-y += ../../../../cpu/x86/tsc
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subdirs-y += ../../../../cpu/intel/microcode
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subdirs-y += ../../../../cpu/intel/microcode
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romstage-y += romstage.c
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romstage-y += romstage.c
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romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
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ramstage-y += chip.c acpi.c cpu.c soc_util.c
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ramstage-y += chip.c acpi.c cpu.c soc_util.c
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ramstage-$(CONFIG_DISPLAY_HOB) += hob_display.c
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ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
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CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/cpx/include -I$(src)/soc/intel/xeon_sp/cpx
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CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/cpx/include -I$(src)/soc/intel/xeon_sp/cpx
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@ -0,0 +1,182 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <fsp/util.h>
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#include <assert.h>
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#include <hob_iiouds.h>
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#include <hob_memmap.h>
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#include <soc/soc_util.h>
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static const uint8_t fsp_hob_iio_uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID;
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static const uint8_t fsp_hob_memmap_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID;
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struct guid_name_map {
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const void *guid;
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const char *name;
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};
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static const struct guid_name_map guid_names[] = {
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{ fsp_hob_iio_uds_guid, "FSP_HOB_IIO_UNIVERSAL_DATA_GUID" },
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{ fsp_hob_memmap_guid, "FSP_SYSTEM_MEMORYMAP_HOB_GUID" },
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};
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const char *soc_get_guid_name(const uint8_t *guid)
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{
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size_t index;
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/* Compare the GUID values in this module */
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for (index = 0; index < ARRAY_SIZE(guid_names); index++)
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if (fsp_guid_compare(guid, guid_names[index].guid))
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return guid_names[index].name;
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return NULL;
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}
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void soc_display_hob(const struct hob_header *hob)
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{
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const struct hob_resource *res;
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res = fsp_hob_header_to_resource(hob);
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assert(res != NULL);
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printk(BIOS_DEBUG, "\tResource type: 0x%x, attribute: 0x%x, addr: 0x%08llx, len: 0x%08llx\n",
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res->type, res->attribute_type, res->addr, res->length);
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printk(BIOS_DEBUG, "\tOwner GUID: ");
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fsp_print_guid(res->owner_guid);
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printk(BIOS_DEBUG, " (%s)\n", fsp_get_guid_name(res->owner_guid));
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if (fsp_guid_compare(res->owner_guid, fsp_hob_iio_uds_guid))
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soc_display_iio_universal_data_hob();
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else if (fsp_guid_compare(res->owner_guid, fsp_hob_memmap_guid))
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soc_display_memmap_hob();
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}
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void soc_display_memmap_hob(void)
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{
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size_t hob_size;
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const struct SystemMemoryMapHob *hob;
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const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID;
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hob = (const struct SystemMemoryMapHob *)fsp_find_extension_hob_by_guid(
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mem_hob_guid, &hob_size);
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assert(hob != NULL);
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printk(BIOS_DEBUG, "===================== MEMORY MAP HOB DATA =====================\n");
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printk(BIOS_DEBUG, "hob: %p\n", hob);
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printk(BIOS_DEBUG, "\tlowMemBase: 0x%x, lowMemSize: 0x%x, highMemBase: 0x%x, "
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"highMemSize: 0x%x\n",
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hob->lowMemBase, hob->lowMemSize, hob->highMemBase, hob->highMemSize);
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printk(BIOS_DEBUG, "\tmemSize: 0x%x, memFreq: 0x%x\n",
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hob->memSize, hob->memFreq);
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printk(BIOS_DEBUG, "\tSystemMemoryMapElement Entries: %d\n", hob->numberEntries);
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for (int e = 0; e < hob->numberEntries; ++e) {
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const struct SystemMemoryMapElement *mem_element = &hob->Element[e];
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printk(BIOS_DEBUG, "\t\tmemory_map %d BaseAddress: 0x%x, ElementSize: 0x%x, Type: 0x%x\n",
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e, mem_element->BaseAddress,
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mem_element->ElementSize, mem_element->Type);
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}
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}
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void soc_display_iio_universal_data_hob(void)
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{
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size_t hob_size;
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const IIO_UDS *hob;
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const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID;
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hob = (const IIO_UDS *)fsp_find_extension_hob_by_guid(
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fsp_hob_iio_universal_data_guid, &hob_size);
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assert(hob != NULL);
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printk(BIOS_DEBUG, "===================== IIO_UDS HOB DATA =====================\n");
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printk(BIOS_DEBUG, "\t===================== SYSTEM STATUS =====================\n");
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printk(BIOS_DEBUG, "\tnumCpus: 0x%x\n", hob->SystemStatus.numCpus);
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printk(BIOS_DEBUG, "\ttolmLimit: 0x%x\n", hob->SystemStatus.tolmLimit);
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printk(BIOS_DEBUG, "\ttohmLimit: 0x%x\n", hob->SystemStatus.tohmLimit);
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printk(BIOS_DEBUG, "\t===================== PLATFORM DATA =====================\n");
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printk(BIOS_DEBUG, "\tPlatGlobalIoBase: 0x%x\n", hob->PlatformData.PlatGlobalIoBase);
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printk(BIOS_DEBUG, "\tPlatGlobalIoLimit: 0x%x\n", hob->PlatformData.PlatGlobalIoLimit);
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printk(BIOS_DEBUG, "\tPlatGlobalMmiolBase: 0x%x\n",
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hob->PlatformData.PlatGlobalMmiolBase);
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printk(BIOS_DEBUG, "\tPlatGlobalMmiolLimit: 0x%x\n",
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hob->PlatformData.PlatGlobalMmiolLimit);
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printk(BIOS_DEBUG, "\tPlatGlobalMmiohBase: 0x%llx\n",
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hob->PlatformData.PlatGlobalMmiohBase);
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printk(BIOS_DEBUG, "\tPlatGlobalMmiohLimit: 0x%llx\n",
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hob->PlatformData.PlatGlobalMmiohLimit);
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printk(BIOS_DEBUG, "\tMemTsegSize: 0x%x\n", hob->PlatformData.MemTsegSize);
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printk(BIOS_DEBUG, "\tMemIedSize: 0x%x\n", hob->PlatformData.MemIedSize);
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printk(BIOS_DEBUG, "\tPciExpressBase: 0x%llx\n", hob->PlatformData.PciExpressBase);
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printk(BIOS_DEBUG, "\tPciExpressSize: 0x%x\n", hob->PlatformData.PciExpressSize);
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printk(BIOS_DEBUG, "\tMemTolm: 0x%x\n", hob->PlatformData.MemTolm);
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printk(BIOS_DEBUG, "\tnumofIIO: 0x%x\n", hob->PlatformData.numofIIO);
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printk(BIOS_DEBUG, "\tMaxBusNumber: 0x%x\n", hob->PlatformData.MaxBusNumber);
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printk(BIOS_DEBUG, "\tIoGranularity: 0x%x\n", hob->PlatformData.IoGranularity);
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printk(BIOS_DEBUG, "\tMmiolGranularity: 0x%x\n", hob->PlatformData.MmiolGranularity);
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printk(BIOS_DEBUG, "\tMmiohGranularity: hi: 0x%x, lo:0x%x\n",
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hob->PlatformData.MmiohGranularity.hi, hob->PlatformData.MmiohGranularity.lo);
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printk(BIOS_DEBUG, "\tPci64BitResourceAllocation: %d\n",
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hob->PlatformData.Pci64BitResourceAllocation);
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for (uint8_t s = 0; s < hob->PlatformData.numofIIO; ++s) {
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printk(BIOS_DEBUG, "\t============ Socket %d Info ================\n", s);
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printk(BIOS_DEBUG, "\tValid: 0x%x\n",
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hob->PlatformData.IIO_resource[s].Valid);
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printk(BIOS_DEBUG, "\tSocketID: 0x%x\n",
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hob->PlatformData.IIO_resource[s].SocketID);
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printk(BIOS_DEBUG, "\tBusBase: 0x%x\n",
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hob->PlatformData.IIO_resource[s].BusBase);
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printk(BIOS_DEBUG, "\tBusLimit: 0x%x\n",
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hob->PlatformData.IIO_resource[s].BusLimit);
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printk(BIOS_DEBUG, "\tPciResourceIoBase: 0x%x\n",
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hob->PlatformData.IIO_resource[s].PciResourceIoBase);
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printk(BIOS_DEBUG, "\tPciResourceIoLimit: 0x%x\n",
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hob->PlatformData.IIO_resource[s].PciResourceIoLimit);
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printk(BIOS_DEBUG, "\tIoApicBase: 0x%x\n",
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hob->PlatformData.IIO_resource[s].IoApicBase);
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printk(BIOS_DEBUG, "\tIoApicLimit: 0x%x\n",
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hob->PlatformData.IIO_resource[s].IoApicLimit);
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printk(BIOS_DEBUG, "\tPciResourceMem32Base: 0x%x\n",
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hob->PlatformData.IIO_resource[s].PciResourceMem32Base);
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printk(BIOS_DEBUG, "\tPciResourceMem32Limit: 0x%x\n",
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hob->PlatformData.IIO_resource[s].PciResourceMem32Limit);
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printk(BIOS_DEBUG, "\tPciResourceMem64Base: 0x%llx\n",
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hob->PlatformData.IIO_resource[s].PciResourceMem64Base);
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printk(BIOS_DEBUG, "\tPciResourceMem64Limit: 0x%llx\n",
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hob->PlatformData.IIO_resource[s].PciResourceMem64Limit);
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printk(BIOS_DEBUG, "\t============ Stack Info ================\n");
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for (int x = 0; x < MAX_LOGIC_IIO_STACK; ++x) {
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const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x];
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printk(BIOS_DEBUG, "\t\t========== Stack %d ===============\n", x);
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printk(BIOS_DEBUG, "\t\tPersonality: 0x%x\n", ri->Personality);
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printk(BIOS_DEBUG, "\t\tBusBase: 0x%x\n", ri->BusBase);
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printk(BIOS_DEBUG, "\t\tBusLimit: 0x%x\n", ri->BusLimit);
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printk(BIOS_DEBUG, "\t\tPciResourceIoBase: 0x%x\n",
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ri->PciResourceIoBase);
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printk(BIOS_DEBUG, "\t\tPciResourceIoLimit: 0x%x\n",
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ri->PciResourceIoLimit);
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printk(BIOS_DEBUG, "\t\tIoApicBase: 0x%x\n", ri->IoApicBase);
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printk(BIOS_DEBUG, "\t\tIoApicLimit: 0x%x\n", ri->IoApicLimit);
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printk(BIOS_DEBUG, "\t\tPciResourceMem32Base: 0x%x\n",
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ri->PciResourceMem32Base);
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printk(BIOS_DEBUG, "\t\tPciResourceMem32Limit: 0x%x\n",
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ri->PciResourceMem32Limit);
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printk(BIOS_DEBUG, "\t\tPciResourceMem64Base: 0x%llx\n",
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ri->PciResourceMem64Base);
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printk(BIOS_DEBUG, "\t\tPciResourceMem64Limit: 0x%llx\n",
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ri->PciResourceMem64Limit);
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printk(BIOS_DEBUG, "\t\tVtdBarAddress: 0x%x\n", ri->VtdBarAddress);
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}
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printk(BIOS_DEBUG, "\t============ PcieInfo ================\n");
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IIO_RESOURCE_INSTANCE iio_resource =
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hob->PlatformData.IIO_resource[s];
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for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) {
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printk(BIOS_DEBUG, "\t\tPort: %d, Device: 0x%x, Function: 0x%x\n",
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p, iio_resource.PcieInfo.PortInfo[p].Device,
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iio_resource.PcieInfo.PortInfo[p].Function);
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}
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}
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}
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@ -42,5 +42,6 @@ int get_threads_per_package(void);
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const struct SystemMemoryMapHob *get_system_memory_map(void);
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const struct SystemMemoryMapHob *get_system_memory_map(void);
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void set_bios_init_completion(void);
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void set_bios_init_completion(void);
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void soc_display_iio_universal_data_hob(void);
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#endif /* _SOC_UTIL_H_ */
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#endif /* _SOC_UTIL_H_ */
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@ -0,0 +1,63 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <fsp/util.h>
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#include <lib.h>
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#define DUMP_UPD(old, new, field) \
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fsp_display_upd_value(#field, sizeof(old->field), old->field, new->field)
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/* Display the UPD parameters for MemoryInit */
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void soc_display_fspm_upd_params(
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const FSPM_UPD *fspm_old_upd,
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const FSPM_UPD *fspm_new_upd)
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{
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const FSP_M_CONFIG *new;
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const FSP_M_CONFIG *old;
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old = &fspm_old_upd->FspmConfig;
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new = &fspm_new_upd->FspmConfig;
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printk(BIOS_DEBUG, "UPD values for MemoryInit:\n");
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DUMP_UPD(old, new, DebugPrintLevel);
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DUMP_UPD(old, new, PchAdrEn);
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hexdump(fspm_new_upd, sizeof(*fspm_new_upd));
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}
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/* Display the UPD parameters for SiliconInit */
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void soc_display_fsps_upd_params(
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const FSPS_UPD *fsps_old_upd,
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const FSPS_UPD *fsps_new_upd)
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{
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const FSPS_CONFIG *new;
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const FSPS_CONFIG *old;
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old = &fsps_old_upd->FspsConfig;
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new = &fsps_new_upd->FspsConfig;
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printk(BIOS_DEBUG, "UPD values for SiliconInit:\n");
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DUMP_UPD(old, new, BifurcationPcie0);
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DUMP_UPD(old, new, BifurcationPcie1);
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DUMP_UPD(old, new, ActiveCoreCount);
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DUMP_UPD(old, new, CpuMicrocodePatchBase);
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DUMP_UPD(old, new, CpuMicrocodePatchSize);
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DUMP_UPD(old, new, EnablePcie0);
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DUMP_UPD(old, new, EnablePcie1);
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DUMP_UPD(old, new, EnableEmmc);
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DUMP_UPD(old, new, EnableGbE);
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DUMP_UPD(old, new, FiaMuxConfigRequestPtr);
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DUMP_UPD(old, new, PcieRootPort0DeEmphasis);
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DUMP_UPD(old, new, PcieRootPort1DeEmphasis);
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DUMP_UPD(old, new, PcieRootPort2DeEmphasis);
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DUMP_UPD(old, new, PcieRootPort3DeEmphasis);
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DUMP_UPD(old, new, PcieRootPort4DeEmphasis);
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DUMP_UPD(old, new, PcieRootPort5DeEmphasis);
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DUMP_UPD(old, new, PcieRootPort6DeEmphasis);
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DUMP_UPD(old, new, PcieRootPort7DeEmphasis);
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DUMP_UPD(old, new, EMMCDLLConfigPtr);
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hexdump(fsps_new_upd, sizeof(*fsps_new_upd));
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}
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