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soc/intel/skylake: Use GPIO state macros from intelblocks/gpio_defs.h 

TEST=Able to build and boot EVE platform.
1) Dump and disassemble DSDT, verify unified methods like GRXS,
GTXS etc. are there
2) Verify no ACPI error seen while running 'dmesg' from console
3) abuild --timeless to ensure there are no other functional changes.

Change-Id: I02df3ddf5ad33d42d97feefb0fa366ad8c856565
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45681
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2020-09-24 13:54:35 +05:30
parent eab9e86733
commit ed6604d1f5
1 changed files with 5 additions and 7 deletions
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12
src/soc/intel/skylake/acpi/gpio.asl
View File

@ -1,9 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <intelblocks/gpio_defs.h>
#include <soc/gpio.h>
#define GPIOTXSTATE_MASK 0x1
#define GPIORXSTATE_MASK 0x1
Device (GPIO)
{
Name (_HID, "INT344B")
@ -119,7 +117,7 @@ Method (GRXS, 1, Serialized)
{
VAL0, 32
}
Local0 = GPIORXSTATE_MASK & (VAL0 >> PAD_CFG0_RX_STATE_BIT)
Local0 = (PAD_CFG0_RX_STATE & VAL0) >> PAD_CFG0_RX_STATE_BIT
Return (Local0)
}
@ -135,7 +133,7 @@ Method (GTXS, 1, Serialized)
{
VAL0, 32
}
Local0 = GPIOTXSTATE_MASK & VAL0
Local0 = PAD_CFG0_TX_STATE & VAL0
Return (Local0)
}
@ -151,7 +149,7 @@ Method (STXS, 1, Serialized)
{
VAL0, 32
}
VAL0 |= GPIOTXSTATE_MASK
VAL0 |= PAD_CFG0_TX_STATE
}
/*
@ -165,5 +163,5 @@ Method (CTXS, 1, Serialized)
{
VAL0, 32
}
VAL0 &= ~GPIOTXSTATE_MASK
VAL0 &= ~PAD_CFG0_TX_STATE
}