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device/pciexp_device: Convert LTR non-snoop/snoop value into common macro 

Change-Id: I3d14a40b4ed0dcc216dcac883e33749b7808f00d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
This commit is contained in:
Subrata Banik 2019-03-25 21:49:39 +05:30
parent e651e01518
commit ed6996f2ba
3 changed files with 10 additions and 7 deletions
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5
src/include/device/pciexp.h
View File

@ -14,6 +14,11 @@ enum aspm_type {
#define ASPM_LTR_L12_THRESHOLD_SCALE_OFFSET 29 #define ASPM_LTR_L12_THRESHOLD_SCALE_OFFSET 29
#define ASPM_LTR_L12_THRESHOLD_SCALE_MASK (0x7 << ASPM_LTR_L12_THRESHOLD_SCALE_OFFSET) #define ASPM_LTR_L12_THRESHOLD_SCALE_MASK (0x7 << ASPM_LTR_L12_THRESHOLD_SCALE_OFFSET)
/* Latency tolerance reporting, max non-snoop latency value 3.14ms */
#define PCIE_LTR_MAX_NO_SNOOP_LATENCY_3146US 0x1003
/* Latency tolerance reporting, max snoop latency value 3.14ms */
#define PCIE_LTR_MAX_SNOOP_LATENCY_3146US 0x1003
void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,
unsigned int max_devfn); unsigned int max_devfn);

4
src/soc/intel/broadwell/pcie.c
View File

@ -652,7 +652,9 @@ static void pch_pcie_enable(struct device *dev)
static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int off) static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int off)
{ {
/* Set max snoop and non-snoop latency for Broadwell */ /* Set max snoop and non-snoop latency for Broadwell */
pci_write_config32(dev, off, 0x10031003); pci_write_config32(dev, off,
PCIE_LTR_MAX_NO_SNOOP_LATENCY_3146US << 16 |
PCIE_LTR_MAX_SNOOP_LATENCY_3146US);
} }
static struct pci_operations pcie_ops = { static struct pci_operations pcie_ops = {

8
src/soc/intel/common/block/pcie/pcie.c
View File

@ -21,10 +21,6 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#define CACHE_LINE_SIZE 0x10 #define CACHE_LINE_SIZE 0x10
/* Latency tolerance reporting, max non-snoop latency value 3.14ms */
#define PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE 0x1003
/* Latency tolerance reporting, max snoop latency value 3.14ms */
#define PCIE_LTR_MAX_SNOOP_LATENCY_VALUE 0x1003
static void pch_pcie_init(struct device *dev) static void pch_pcie_init(struct device *dev)
{ {
@ -66,8 +62,8 @@ static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset)
{ {
/* Set max snoop and non-snoop latency for the SOC */ /* Set max snoop and non-snoop latency for the SOC */
pci_write_config32(dev, offset, pci_write_config32(dev, offset,
PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE << 16 | PCIE_LTR_MAX_NO_SNOOP_LATENCY_3146US << 16 |
PCIE_LTR_MAX_SNOOP_LATENCY_VALUE); PCIE_LTR_MAX_SNOOP_LATENCY_3146US);
} }
static struct pci_operations pcie_ops = { static struct pci_operations pcie_ops = {