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soc/intel/tgl: Add configurable value for ConfigTdpLevel 

According to Tigerlake TDP specifications (doc #575683, table 4-2),
TGL supports different TDP levels depends on CPU segement/package,
IA Cores and graphics configuration. For example, UP3 4-Core GT2
suppots base TDP=28W, Configurable TDP-Down_1=15W and Configurable
TDP-Down_2=12W. This configurable value can be used to select
suitable TDP level

Change-Id: I4242575807caac172b6cbe667839bf6c9241f3c5
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Derek Huang 2021-01-27 17:01:00 +08:00 committed by Tim Wawrzynczak
parent e65e9dd6b1
commit ed6bda2818
2 changed files with 10 additions and 2 deletions
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3
src/soc/intel/tigerlake/chip.h
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@ -105,6 +105,9 @@ struct soc_intel_tigerlake_config {
/* Common struct containing power limits configuration information */ /* Common struct containing power limits configuration information */
struct soc_power_limits_config power_limits_config[POWER_LIMITS_MAX]; struct soc_power_limits_config power_limits_config[POWER_LIMITS_MAX];
/* Configuration for boot TDP selection; */
uint8_t ConfigTdpLevel;
/* Gpio group routed to each dword of the GPE0 block. Values are /* Gpio group routed to each dword of the GPE0 block. Values are
* of the form PMC_GPP_[A:U] or GPD. */ * of the form PMC_GPP_[A:U] or GPD. */
uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */

9
src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
View File

@ -1304,9 +1304,14 @@ typedef struct {
**/ **/
UINT8 IsTPMPresence; UINT8 IsTPMPresence;
/** Offset 0x0389 - Reserved /** Offset 0x0389 - ConfigTdpLevel
Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP Up;0xFF : Deactivate
**/ **/
UINT8 Reserved17[6]; UINT8 ConfigTdpLevel;
/** Offset 0x038A - Reserved
**/
UINT8 Reserved17[5];
/** Offset 0x038F - Enable PCH HSIO PCIE Rx Set Ctle /** Offset 0x038F - Enable PCH HSIO PCIE Rx Set Ctle
Enable PCH PCIe Gen 3 Set CTLE Value. Enable PCH PCIe Gen 3 Set CTLE Value.